• Title/Summary/Keyword: balun transformer

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Design of a Two-stage Differential cascode Power Amplifier with a Temperature Compensation function of High PAE with 2.4 GHz (2.4GHz 대역폭을 갖는 온도 보상 기능 탑재 고전력부가효율의 2 단 차동 캐스코드 전력증폭기 설계 )

  • Joon Hyung Park;Jisung Jang;Howon Kim;Kang-Yoon Lee
    • Transactions on Semiconductor Engineering
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    • v.2 no.3
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    • pp.6-12
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    • 2024
  • This paper presents a study on a 2.4GHz differential cascode power amplifier(PA) fabricated using a 130nm CMOS process. This PA is designed for wireless power transmission applications and consists of two differential stages with custom-designed balun transformers for single-ended output. Balun transformers are utilized not only for the output stage but also for power match-ing between each stage. Additionally, a bias circuit with temperature compensation capability is added to maintain stable bias voltage in the 2.4GHz frequency band. As a result, it achieves an output power of 21.75 dBm with a power-added efficiency(PAE) of 40.9% at TT/40℃.

Design of a V Band Power Amplifier Using 65 nm CMOS Technology (65 nm CMOS 공정을 이용한 V 주파수대 전력증폭기 설계)

  • Lee, Sungah;Cui, Chenglin;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.4
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    • pp.403-409
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    • 2013
  • In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

High-Efficiency CMOS Power Amplifier Using Uneven Bias for Wireless LAN Application

  • Ryu, Namsik;Jung, Jae-Ho;Jeong, Yongchae
    • ETRI Journal
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    • v.34 no.6
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    • pp.885-891
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    • 2012
  • This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

A Fully Integrated 5-GHz CMOS Power Amplifier for IEEE 802.11a WLAN Applications

  • Baek, Sang-Hyun;Park, Chang-Kun;Hong, Song-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.2
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    • pp.98-101
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    • 2007
  • A fully integrated 5-GHz CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using $0.18-{\mu}m$ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of $1.7mm{\times}1.2mm$. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-dBm output 1-dB compression point, 23.8-dBm saturated output power, 25-dB power gain. The measured power added efficiency (PAE) is 20.1 % at max. peak, 18.8% at P1dB. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12dBm of average power at the EVM of -25dB.

유도 결합 플라즈마에서 밸런스 파워에 의한 전자밀도의 증가 효과

  • Kim, Hyeon-Jun;Choe, Ik-Jin;Lee, Yeong-Gwang;Jeong, Jin-Uk
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.219-219
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    • 2011
  • 공정용 유도 결합 플라즈마(ICP)에서 강자성체인 페라이트를 이용하여 제작한 발룬 변압기(balun transformer)를 사용하여 플라즈마 밀도를 높이는 실험을 수행하였다. 실험에서는 2개의 발룬 변압기를 이중구조 안테나에 설치하여 실제 인가되는 전압이 접지전위 대비+V에서 ${\pm}$V/2로 변환되도록 구성하였다. 20~100 mTorr 압력 범위의 아르곤 기체 50 sccm에 30~70 W범위의 전력을 인가하여 반응용기의 중앙과 벽면에서 부유 탐침법을 적용하여 플라즈마 밀도를 측정 하였다. 같은 압력과 같은 전력에서 발룬 변압기를 사용했을 때와 회로에서 변압기만 제거한 실험을 비교하면 반응용기 중앙에서 플라즈마 밀도가 평균 10% 증가함을 보였다. 이는 안테나에 발란스 된 전압이 인가되면 플라즈마 균일도가 증가하고 부유전위(floating potential) 대비 플라즈마 전위(plasma potential)가 낮아져서 이온에 의한 손실이 줄어들어 전자가 더 많은 에너지를 흡수해서 나타나는 현상이다. 특히 E-mode에서 H-mode로 전환되면 플라즈마 밀도가 크게 증가함을 보였고, 반응용기 벽면에서는 발룬 변압기를 사용했을 때 밀도가 낮다가 H-mode로 전환 시 비교실험 대비 밀도가 크게 증가함을 볼 수 있었다.

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Design of High-Power and High-Efficiency Broadband Amplifier Using 1:4 Transmission Line Transformer (1:4 전송 선로 트랜스포머를 이용한 고출력 고효율 광대역 전력 증폭기의 설계)

  • Kim, Kyung-Won;Seo, Min-Cheol;Cho, Jae-Yong;Yoo, Sung-Cheol;Kim, Min-Su;Kim, Hyung-Cheol;Oh, Jun-Hee;Sim, Jae-Woo;Yang, Youn-Goo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.2
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    • pp.121-128
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    • 2010
  • This paper presents a design of a 100 W high-efficiency power amplifier, whose operational frequency band expands from 30 to 512 MHz, using negative feedback network, push-pull structure, broadband RF choke, and transmission line transformer for balun configuration. The push-pull amplifier has been tuned for higher output power using a shunt capacitor as a matching component at its load especially for high-frequency region. The implemented power amplifier exhibited a very flat power gain of $18.34{\pm}0.9\;dB$ throughout the operating frequency band and very high power-added efficiency(PAE) of greater than 40% at an output power of 100 W. It also showed second- and third-harmonic distortion levels of below -34 dBc and -12 dBc, respectively, through the entire operating frequency band.

Design of PCB Embedded Balanced-to-unbalanced WiMax Duplexer Using Coupled LC Resonators (WiMAX 응용을 위한 결합 공진기 기반의 PCB 내장형 평형신호 듀플렉서의 설계)

  • Park, Ju-Y.;Park, Jong-C.;Park, Jae-Y.
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1587_1588
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    • 2009
  • In this paper, PCB embedded balanced-to-unbalamced duplexer using coupled LC resonator was introduced for low cost dualband WiMax front-end-module application. In order to obtain the function of bandpass filter and balun transformer, proposed duplexer was configured by using magnetically coupled LC resonator. Out-of-band suppression was enhanced by applying two m-Derived transform circuits to obtain transmission zeros at 2GHz and 4.8GHz. In order to reduce the size of embedded duplexer, BaSrTiO3 (BST) composite high Dk RCC film was applied to improve the capacitance density. This high Dk film provided the capacitance density of 12.2 pF/mm2. The simulation results shows that fabricated duplexer had an insertion loss of 2.9dB and 5.5dB and return loss of 15dB and 16dB for 2.5GHz~2.6GHz and 3.5GHz~3.6GHz, respectively. The maximum magnitude and phase imbalance were 0.01dB and 0.17dB, and 1degree and 2degree in its passband, respectively. The out-of-band suppression was observed approximately 29dB and 40dB below 1.9GHz and over 4.5GHz, respectively. It has a volume of 6 mm $\times$ 7 mm $\times$ 0.7 mm (height).

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High-Efficiency CMOS Power Amplifier using Low-Loss PCB Balun with Second Harmonic Impedance Matching (2차 고조파 정합 네트워크를 포함하는 저손실 PCB 발룬을 이용한 고효율 CMOS 전력증폭기)

  • Kim, Hyungyu;Lim, Wonseob;Kang, Hyunuk;Lee, Wooseok;Oh, Sungjae;Oh, Hansik;Yang, Youngoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.30 no.2
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    • pp.104-110
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    • 2019
  • In this paper, a complementary metal oxide semiconductor(CMOS) power amplifier(PA) integrated circuit operating in the 900 MHz band for long-term evolution(LTE) communication systems is presented. The output matching network based on a transformer was implemented on a printed circuit board for low loss. Simultaneously, to achieve high efficiency of the PA, the second harmonic impedances are controlled. The CMOS PA was fabricated using a $0.18{\mu}m$ CMOS process and measured using an LTE uplink signal with a bandwidth of 10 MHz and peak to average power ratio of 7.2 dB for verification. The implemented CMOS PA module exhibits a power gain of 24.4 dB, power-added efficiency of 34.2%, and an adjacent channel leakage ratio of -30.1 dBc at an average output power level of 24.3 dBm.