• ETRI Journal
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• v.33 no.5
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• pp.818-821
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• 2011

A D-band subharmonically-pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a $180^{\circ}$ power divider structure consisting of a Lange coupler followed by a ${\lambda}$/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs-based metamorphic high electron mobility transistor process with 100-nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4-dBm LO drive and an intermediate frequency of 100 MHz. The input 1-dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.239-244
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• 2004

In this paper, we have developed a frequency mixer which can be used as a microwave phase conjugator in the LS band retrodirective antenna system. The mixer as a phase conjugator must have an If signal of which frequency is nearly as high as that of an RF signal, so this fact brings difficulty in the combination of input signals and the design of impedance matching circuit. The circuit configuration is chosen to be of the gate mixer using a pseudomorphic HEMT device. The operating frequencies are 4.00 ㎓, 2.01 ㎓, and 1.99 ㎓ for LO, RF, and IF, respectively. Conversion gain is measured to be 12.5 ㏈ and 1 ㏈ compression point -34 ㏈m at the LO power of -7 ㏈m. The mixer fabricated in this research is the single-ended type, where RF leakage signal appears inevitably at the If port because RF and If frequencies are almost the same. The circuit topology suggested here can be applied directly to the design of balanced-type mixers and phase conjugators.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.9
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• pp.851-855
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• 2005

We investigated the unbalanced characteristics of the superconducting fault current limiters (SFCLs) based on YBCO thin films with a single line-to-ground fault. When a single line-to-ground fault occurred, the short circuit current of a fault phase increased about 6 times of transport currents after the fault onset but was effectively limited to the designed current level within 2 ms by the resistance development of the SFCL. The fault currents of the sound phases almost did not change because of their direct grounding system. The unbalanced rates of a fault phase were distributed from 6.4 to 1.4. It was found that the unbalanced rates of currents were noticeably improved within one cycle after the fault onset. We calculated the zero phase currents for a single line-to-ground fault using the balanced component analysis. The positive sequence resistance was reduced remarkably right after the fault onset but eventually approached the balanced positive resistance component prior to the system fault. This means that the system reaches almost the three-phase balanced state in about 60 ms after the fault onset at the three-phase system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.6
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• pp.1-5
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• 1977

The input equivalent resistances and operating properties of a transless double balanced modulator are quantitatively investigated in considerations of the nonlinear characteristics of diodes. The input equivalent resistances are derived from the power loss calculations of the circuit. Carrier suppression and modulation efficiency are calculated by using approximate equations which describe the dynamic curves of the diode circuits. The results are represented as a function of the voltage amplitude of a carrier signal owing to the nonlinear characteristics of diodes.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.12
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• pp.624-629
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• 2002

This paper presents the first Simulation model using EMTDC program to analyze the electrified train voltage distribution characteristics in ac auto-transformer 1110 railroads. In general, all of the electrified train supply system has the characteristics that the train supply line is a naturally non-symmetrical and unbalanced system. Also, it is needed to model the Scott transformer which invert the balanced 3-phase quantity into 2-phase. Therefore, the general simulation methodology using previous simplified equivalent circuit or RMS based program can't obtain the accurate results to reflect the real-time operation because these methodology is basically assumed on completely 3-phase balanced system. To overcome these defects, in this paper, the EMTDC simulation model to analysis the completely electrified railroad system with Scott transformer and AC auto-transformer is presented. Also, the correctness of EMTDC modeling is confirmed by the old basic concepts and we think that this EMTDC model has the future powerful capability for application of railroad system analysis.

• Journal of the Korean Society for Railway
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• v.5 no.4
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• pp.253-259
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• 2002

This paper presents the first simulation model using EMTDC program to analyze the electrified train voltage distribution characteristics in ac auto-transformer fed railroads. In general, all of the electrified train supply system has the characteristics that the train supply line is a naturally non-symmetrical and unbalanced system. Also, it is needed to model the Scott transformer which invert the balanced 3-phase quantity into 2-phase. Therefore, the general simulation methodology using previous simplified equivalent circuit or RMS based program can't obtain the accurate results to reflect the real-time operation because these methodology is basically assumed on completely 3-phase balanced system. To overcome these defects, in this paper, the EMTDC simulation model to analysis the completely electrified railroad system with Scott transformer and AC auto-transformer is presented. Also, the correctness of EMTDC modeling is confirmed by the old basic concepts and we think that this EMTDC model has the future powerful capability for application of railroad system analysis.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.2
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• pp.148-152
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• 2010

The superconducting fault current limiter (SFCL) applied into the neural line of a power system, which can limit the unsymmetrical fault current from the single-line ground fault or the double-line ground fault, was reported to be the effective application location of the SFCL in a power system. However, the limiting operation for the symmetrical fault current like the triple line-ground fault is not effective because of properties of the balanced three-phase system. In this paper, the limiting method of the symmetrical fault current in a power system with a SFCL applied into neutral line was suggested. Through the short-circuit experiments of the three-phase fault types for the suggested method, the fault current limiting and recovery characteristics of the SFCL in the neutral line were analyzed and the effectiveness of the suggested method was described.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.6
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• pp.403-410
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• 2000

This paper deals with a study to improve the performance of Moving Coil type Linear Oscillatory Actuator (MC-LOA) considering unbalanced magnetic circuit. MC-LOA has an unbalanced magnetic circuit due to its asymmetric structure. In this type of LOA, the airgap flux density tends to have different magnitude along mover's displacement and the current directions. The above property causes eccentric of displacement center and interferes with the proper oscillation of LOA. Therefore, this paper presents two models having the unbalanced magnetic circuit and the other balanced by the saturated core. In order to compare the characteristics between the two models, a characteristic analysis for both the basic model and the improved model is performed by their dynamic analysis composed of kinetic and electric equations and Finite Element Method (FEM). The propriety of the improved model is verified through the experimental results.

• Journal of Power Electronics
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• v.14 no.4
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• v.18 no.1
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• pp.56-69
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• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.