• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.212-216
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• 2001

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.

• Journal of Power Electronics
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• v.2 no.2
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• pp.139-145
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• 2002

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitice between the drain/collertor of an active switch and frame ground through its heat sink may generate the commom-mode conducted noise. We have proposed a balanced switching converter circuit, whitch is an effective way to reduce the commom-mode converter version of the balanced switching converter was presented and the mechanism of the commom-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switch converter circuit and presents a buck-boost converter version of the blanced switching converter. The feature of common-mode niose reduction is confirmed by experimental resuits and the mechanisem of the commom-mode niose reduction is explained using equivalent circuits.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.106-113
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• 1997

A 3V CMOS continuous-time fully-balanced integrator for low-voltage analog-digital mixed-mode signal processing is designed in this paper. The basic architecture of the designed fully-balanced integrator is complementary circuit which is composed of NMOS and PMOS transistor. And this complementary circuit can extend transconductance of an integrator. So. the unity gain frequency, pole and zero of integrator are increased by the extended transconductance. The SPICE simulation and small signal analysis results show that the UGF, pole and zero of the integrator is increased larger than those of the compared integrtors. The three-pole active low-pass filter is designed as a application circuit of the fully-balanced integrator, using 0.83V CMOS processing parameter.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.479-482
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• 1993

A fully balanced differential amplifier can achieve high-gain wide-bandwidth characteristics. And also, Offset PSRR, CMRR and Noise performance of that are excellent, but these merits can be achieved only when the architecture holds fully balanced. Commonly, the fully balanced differential amplifier has a common mode feedback(CMFB) circuit in order to maintain the balance. This paper presents improved characteristics of the CMFB circuit and designs the wide-bandwidth CMOS Op-amp. The unity gain bandwidth of this Op-amp is 50MHz with the load capacitor 2pF, and the value of phase margin is $85^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.4
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• pp.323-331
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• 1997

In this paper, the high efficiency balanced amplifier is presented as high efficiency power amplifier. This amplifier is basically composed of two FETs, an input power divider, output power combiner, input matching circuits, output matching circuits, second harmonic interconnection circuit and lowpass filter. The second harmonic interconnection circuit is composed of second harmonic frequency bandpass filter and transmission line. This circuit is inserted between the output terminals of the two FEF's output matching circuit, there is a second harmonic standing wave generated between two FET outputs. The electric wall termination is equivalent to the short circuit termination. As a result, the FET output termination condition needed to attain high efficiency is realized. Experimental high efficiency balanced amplifier is constructed to determine its practically attainable efficiency. The input VSWR is 1.27, and the output VSWR is 1.18. Power added efficiency of 75% is attained at 1.75 GHz band about 3W to balanced amplifier.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.493-498
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• 2004

The EMI noise source in a switching mode power supply is dominated by a common mode noise. If we can understand the common mode noise occurring mechanism, it is resulted to find out the method to suppress the EMI noise source in the switching mode power supply. The common mode noise is occurring mostly due to circuit is unbalanced which is caused by the capacitive coupling to frame ground, which passes through a heatsink of the switching devices. This research paper presents a new effective balancing method of buck converter circuit by mean of grounding the parasitic and compensation capacitors in correct proportion which is called that the common mode impedance balance (CMIB). The CMIB can be achieved by source, transmission line and termination balanced, such balancing, the common mode current will be cancelled out in the frame ground. The greatly reduced common mode noise can be confirmed by the experimental results.

• Journal of Power Electronics
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• v.11 no.4
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• pp.520-526
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• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.

• Journal of the Korea Convergence Society
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• v.11 no.10
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• pp.63-69
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• 2020

In this paper, a small microwave sensor that can be applied to a wearable device is proposed because it can detect the heartbeat signal of a human body moving irregularly at low speed. It consist of balanced microstrip radiation patches in the 2.4 GHz ISM band, self-oscillation detection circuit, and feedback circuit. Based on the theoretical development and simulation, the validity of the proposed structure was confirmed and the manufactured prototype was tested. The board size of the circuit is as small as 65mm × 85㎟, and has a low power consumption of 60mW thanks to the simple RF circuit structure. Finally heartbeat signal has been obtained from a human body moving at low speed (0.5Hz) within a linear distance of 2 to 30mm close to the sensor and a lateral distance of ±20mm.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.8
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• pp.409-416
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• 2002

This paper presents a fault location algorithm using direct 3-phase circuit analysis for distribution power networks. The unbalanced feature of distribution networks due to single phase loads or asymmetric operation prohibits us from using the conventional symmetrical component transformation. Even though the symmetrical component transformation provides us with a very easy tool in three phase network analysis, it is limited to balanced systems in utilizing its strong point, which is not suitable for distribution networks. In this paper, a fault location algorithm using direct 3-phase circuit analysis is developed. The algorithm is derived and it Is shown that the proposed method if we use matrix inverse lemma, is not more difficult then the conventional methods using symmetrical component transformation. Since the symmetrical component transformation is not used in the suggested method, unbalanced networks also can be handled with the same difficulty as balanced networks. The case study results show the correctness and effectiveness of the proposed algorithm.