• Title/Summary/Keyword: asynchronous control

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Design of a DI model-based Content Addressable Memory for Asynchronous Cache

  • Battogtokh, Jigjidsuren;Cho, Kyoung-Rok
    • International Journal of Contents
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    • v.5 no.2
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    • pp.53-58
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    • 2009
  • This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

RIX-MAC: An Energy-Efficient Receiver-Initiated Wakeup MAC Protocol for WSNs

  • Park, Inhye;Lee, Hyungkeun;Kang, Seokjoong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.5
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    • pp.1604-1617
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    • 2014
  • This paper proposes RIX-MAC (Receiver-Initiated X-MAC), a new energy-efficient MAC protocol based on an asynchronous duty cycling. RIX-MAC improves energy efficiency through utilizing short preambles and adopting the receiver-initiated approach, where RIX-MAC minimizes sender nodes' energy consumption by enabling transmitters to predict receiver nodes' wake-up times. It also reduces receiver nodes' energy consumption by decreasing the number of control frames. We use the network simulator to evaluate RIX-MAC's performance. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a remarkable improvement in energy-efficiency and end-to-end delay.

Development of Coordinated Scheduling Algorithm and End-to-end Delay Analysis for CAN-based Distributed Control Systems (CAN기반 분산 제어시스템의 종단 간 지연시간 분석과 협조 스케줄링 알고리즘 개발)

  • 이희배;김홍열;김대원
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.7
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    • pp.501-508
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    • 2004
  • In this paper, a coordinated scheduling algorithm is proposed to reduce end-to-end delay in distributed control of systems. For the algorithm, the analysis of practical end-to-end delay in the worst case is performed priory with considering implementation of the systems. The end-to-end delay is composed of the delay caused by multi-task scheduling of operating systems, the delay caused by network communications, and the delay caused by asynchronous timing between operating systems and network communications. Through some simulation tests based on CAN(Controller Area Network), the proposed worst case end-to-end delay analysis is validated. Through the simulation tests, it is also shown that a real-time distributed control system designed to existing worst case delay cannot guarantee end-to-end time constraints. With the analysis, a coordinated scheduling algorithm is proposed here. The coordinated scheduling algorithm is focused on the reduction of the delay caused by asynchronous timing between operating systems and network communications. Online deadline assignment strategy is proposed for the scheduling. The performance enhancement of the distributed control systems by the scheduling algorithm is shown through simulation tests.

Design of Asynchronous Library and Implementation of Interface for Heterogeneous System (비동기 라이브러리 설계와 Heterogeneous시스템을 위한 인테페이스 설계)

  • Jung, Hwi-Sung;Lee, Joon-Il;Lee, Moon-Key
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.9
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    • pp.47-54
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    • 2000
  • We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

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A Study on the Application of Asynchronous Team Theory for QVC and Security Assessment in a Power System (전력계통의 무효전력 제어 및 안전도 평가를 위한 Asynchronous Team 이론의 적용에 관한 연구)

  • 김두현;김상철
    • Journal of the Korean Society of Safety
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    • v.12 no.3
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    • pp.67-75
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    • 1997
  • This paper presents a study on the application of Asynchronous Team(A-Team) theory for QVC(Reactive power control) and security assessment in a power system. Reactive power control problem is the one of optimally establishing voltage level given reactive power sources, which is very important problem to supply the demand without interruption and needs methods to alleviate a bus voltage limit violation more quickly. It can be formulated as a mixed-integer linear programming(MILP) problem without deteriorating of solution accuracy to a certain extent. The security assessment is to estimate the relative robustness of the system and deterministic approach based on AC load flow calculations is adopted to assess it, especially voltage security. A distance measure, as a measurement for voltage security, is introduced. In order to analyze the above two problem, reactive power control and static security assessment, In an integrated fashion, a new organizational structure, called an A-team, is adopted. An A-team is well-suited to the development of computer-based, multi-agent systems for operation of large-scaled power systems. In order to verify the usefulness of the suggested scheme herein, modified IEEE 30 bus system is employed as a sample system. The results of a case study are also presented.

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Model Matching for Input/Output Asynchronous Machines Using Output Equivalent Machines (출력 등가 머신을 이용한 비동기 순차 머신의 모델 정합)

  • Park, Yong Kuk;Yang, Jung-Min
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.173-181
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    • 2014
  • This paper addresses the problem of model matching control for a class of systems modeled as input/output asynchronous sequential machines. Based on the feedback control scheme, we design a corrective controller that compensates the behavior of the closed-loop system so as to match a reference model. Whereas the former studies use state observers and the output burst for designing a controller, the present research needs neither the observer nor the output burst in controller design. We define the 'output equivalent machine' of the considered machine to describe the existence condition and the construction algorithm for the proposed controller. A case study is provided to show the operation of the proposed corrective controller.

A Modeling Technique for Performance Evaluation of Asynchronous TMR Controller (비동기 3중화 제어기의 성능분석을 위한 모델링 기법)

  • Kim, Seog-Joo;Kwon, Soon-Man;Kim, Jong-Moon;Kim, Kook-Hun
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.2684-2686
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    • 2000
  • This paper describes a preliminary study on a modeling technique for control performance evaluation of asynchronous TMR(Triple Modular Redundancy) controller. Hybrid system modeling is applied to TMR controller performance evaluation and mixed logical dynamical system description is used to model the behavior of majority voter in the controller. Windup and bumpless transfer problems in redundancy controls are also mentioned.

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Implementation and Analysis of Asynchronous data and Control data capture application in MOST Network (MOST Network의 Asynchronous data와 control data 캡처 application 구현 및 분석)

  • Kim, Seon-Nam;Kwak, Gil-Bong;Ahn, Gwi-Im
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.427-430
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    • 2010
  • MOST Network는 오디오와 비디오 데이터를 실시간으로 전송하는 동기식데이터 영역과 패킷데이터를 전송하는 비동기식 데이터 영역, 네트워크 관리를 위한 명령, 상태, 진단 정보를 전송하는 control Channel로 구성되어 있다. 본 논문에서는 비동기식 데이터 영역과 Control Channel의 데이터를 캡처 및 분석하는 모듈을 설계 및 구현한 후 실제 MOST 네트워크를 구축하여 검증해 보았다. 구현한 시스템을 바탕으로 고가의 장비를 별도로 보유하지 않더라도 MOST Network의 비동기식 데이터 영역과 Control Channel의 데이터를 확인할 수 있으며, 분석이 가능한 시스템을 제안하였다.

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A Study Mode of Synchronous & Asynchronous for Multimedia Distance Education System (동기 및 비동기 겸용모드의 멀티미디어 원격교육 시스템 개발에 관한 연구)

  • Kim, Sang-Jin;Kim, Seok-Soo;Park, Gil-Cheol;Hwang, Dae-Joon
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.12
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    • pp.2985-2995
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    • 1997
  • In this paper, we proposed the "synchronous & asynchronous distance education system" which is able to interact among teachers and students for open education in cyberspace, and it is based telecommunication technology and multimedia technology. Specially, This system gets rid of the nufamiliarity and inconvenient feeling during the distance education. Also it supports the mediation of floor mode, for a group lecture and supports the synchronous mode for face-to-face effective and asynchronous mode for self-learning. The asynchronous mode has the down load function and the consultant mode (between teacher and student). The element technologies of this system consists of application sharing technique, whiteboard, various video window display, audio support, user interface, environment setup, session management, access control, network control and media control for collaborative distance education.

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Machine Learning-Based Filter Parameter Estimation for Inertial/Altitude Sensor Fusion (관성/고도 센서 융합을 위한 기계학습 기반 필터 파라미터 추정)

  • Hyeon-su Hwang;Hyo-jung Kim;Hak-tae Lee;Jong-han Kim
    • Journal of Advanced Navigation Technology
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    • v.27 no.6
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    • pp.884-887
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    • 2023
  • Recently, research has been actively conducted to overcome the limitations of high-priced single sensors and reduce costs through the convergence of low-cost multi-variable sensors. This paper estimates state variables through asynchronous Kalman filters constructed using CVXPY and uses Cvxpylayers to compare and learn state variables estimated from CVXPY with true value data to estimate filter parameters of low-cost sensors fusion.