• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1090-1100
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• 2017

This paper presents the comparison of starting current characteristics of a three-phase induction motor fed by two types of soft starters. The first soft starter under investigation is a conventional AC voltage controller on the basis of a phase-control technique. The other is the proposed asynchronous PWM AC chopper which is developed from the conventional synchronous PWM AC chopper. In this paper, the proposed asynchronous PWM AC chopper control scheme is developed by generating only two asynchronous PWM signals for a three-phase main power circuit (6 switching devices) from a single voltage control signal which is compared with a single sawtooth carrier signal. By this approach, the PWM signals are independent and easy to implement since the PWM signals do not need to be synchronized with a three-phase voltage source. Details of both soft starters are discussed. The experimental and simulation results of the starting currents are shown. It is found that the asynchronous PWM AC chopper efficiently works as a suitable soft starter for the three-phase induction motor due to that the starting currents are reduced and are sinusoidal with less harmonic contents, when being compared with the starting current waveforms using the conventional phase-control starting technique. Also the proposed soft starter offers low starting electromagnetic torque pulsation.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• ETRI Journal
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• v.35 no.1
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• pp.35-40
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• 2013

Asynchronous ranging is one practical method to implement a locating system that provides accurate results. However, a locating system utilizing asynchronous ranging generates a large number of messages that cause transmission delays or failures and degrades the system performance. This paper proposes a novel approach for efficient congestion control in an asynchronous range-based locating system. The proposed method significantly reduces the number of messages generated during the reader discovery phase by eavesdropping on other transmissions and improves the efficiency of ranging by organizing the tags in a hierarchical fashion in the measurement phase. Our evaluation shows that the proposed method reduces the number of messages by 70% compared to the conventional method and significantly improves the success rate of ranging.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.625-630
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• 2014

Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.9
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• pp.812-818
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• 2012

In this paper, we propose an asynchronous behavior control algorithm of the swarm robot for surrounding intruders when detected an intruder in a surveillance environment. The proposed method is divided into three parts: First, we proposed the method for the modeling of a state of the swarm robot. Second, we proposed an asynchronous behavior control algorithm for the surrounding an intruder by the swarm robot. Third, we proposed a control method for the collision avoidance with the swarm robot. Finally, we show the effectiveness and feasibility of the proposed method through some experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.873-875
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• 2014

In this paper we describe an asynchronous MAC protocol with receiver-initiated duty cycling for energy-efficiency in wireless sensor networks(WSN). Legacy asynchronous MAC protocols, X-MAC and PW-MAC, has weaknesses which generates too many control packets and has data collision problem between multiple transmitters, respectively. Therefore, we propose a receiver-initiated asynchronous MAC protocol which generates control packets from transmitter to complement these disadvantages. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a improvement in energy-efficiency, throughput and latency from simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.177.2-177
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• 2001

The asynchronous gyro outputs in the 3-axis navigation system are defined as each of gyros has its own output frequency. In this case, the navigation system has gyro outputs concurrently with the sensor mechanical frequency instead of the attitude frequency. So, there is an asynchronous error between gyro outputs and attitude calculation. In this paper, we analyze the gyro output error caused by the asynchronous gyro and present the high speed sampling technique and the extrapolation and interpolation of gyro outputs for synchronizing the gyro outputs.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.931-933
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• 2004

In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.