• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5449-5464
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• 2018

Recent works have validated the possibility of reducing the energy consumption in wireless heterogeneous networks, achieved by switching on/off some base stations (BSs) dynamically. In this paper, to realize energy conservation, the discrete time Markov Decision Process (DTMDP) is developed to match up the BS switching operations with the traffic load variations. Then, an asynchronous decision-making algorithm, which is based on the Bellman equation and the on/off priorities of the BSs, is firstly put forward and proved to be optimal in this paper. Through reducing the state and action space during one decision, the proposed asynchronous algorithm can avoid the "curse of dimensionality" occurred in DTMDP frequently. Finally, numerical simulations are conducted to validate the effectiveness and advantages of the proposed asynchronous on/off strategies.

• Journal of Internet Computing and Services
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• v.4 no.5
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• pp.51-60
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• 2003

Asynchronous iteration is a way to reduce performance degradation of some parallel algorithms due to load imbalance or transmission delay between computing nodes, which requires asymmetric communication between the nodes of different speeds. To implement such asynchronous communication on distributed memory systems, we suggest an MPMD method that creates an additional separate server process on each computing node, and compare it with an SPMD method that creates a single process per node.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1380-1386
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• 2011

The request of interrupt accompanies a context switching. If the interrupt is frequently requested, this overhead of context switching can reduce seriously the performance of embedded systems. In order to reduce processing overhead due to frequently requested communication interrupts at Asynchronous Serial Communication, this paper introduces the method of Expanded Asynchronous Serial Communication with the Interrupt Coalescence(IC) that accumulates a fixed number of interrupts and processes them in one time. we implement the existing Asynchronous Serial Communication that requests communication interrupts by one byte at an LN2440SBC embedded board with a uC/OS-II and compare interrupt processing time for the performance evaluation about proposed method. As a result, the communication interrupt processing time of proposed method appears in case of low speed(9,600 bps), the decline of an average 25.18% at transmission, the decline of an average 41.47% at reception. and in case of hight speed(115,200 bps), the decline of an average 16.67% at transmission, the decline of an average 25.61% at reception.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.221-225
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• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.28-37
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• 2010

In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1834-1844
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• 1996

In asynchronous communication data of specific area are used as all kinds of control characters. Therefore, data of this area must be converted to other character and transmitted followed by control prefix to prevent the misconception as control characters. This paper presents several methods for character conversion that prevent the lengthening of data and enhance the overall efficiency of communication by transmitting with a certain conversion and without control prefixes on control-like characters occurring when data are transmitted with ciphering onto asynchronous communication path. For such conversion, the scope of transmitted data was sup-posed and efforts were made not to exceed that scope. Experiments showed that method is better in communication speed than the existing ones and the ciphering has no problem by confirming the randomness of ciphered data.

• Journal of Computing Science and Engineering
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• v.7 no.4
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• pp.231-241
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• 2013

Improvements in wireless sensor network (WSN) technology have resulted in a large number of applications. WSNs have been mainly used for monitoring applications, but they are also applicable to target tracking, health care, and monitoring with multimedia data. Nodes are generally deployed in environments where the exhausted batteries of sensor nodes are difficult to charge or replace. The primary goal of communication protocols in WSNs is to maximize energy efficiency in order to prolong network lifetime. In this paper, various medium access control (MAC) protocols for synchronous/asynchronous and single/multi-channel WSNs are investigated. Single-channel MAC protocols are categorized into synchronous and asynchronous approaches, and the advantages and disadvantages of each protocol are presented. The different features required in multi-channel WSNs compared to single-channel WSNs are also investigated, and surveys on multi-channel MAC protocols proposed for WSNs are provided. Then, existing broadcast schemes in such MAC protocols and efficient multi-hop broadcast protocols proposed for WSNs are provided. The limitations and challenges in many communication protocols according to this survey are pointed out, which will help future researches on the design of communication protocols for WSNs.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.