• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1057-1065
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• 2011

In order to achieve the ease of development and to facilitate the maintenance of codes for complex Ajax (Asynchronous Java Script and XML)-based web clients, this paper proposes a CVC (Communicator-View-Controller) architecture pattern by modifying the well-known MVC (Model-View-Controller) framework. By composing the Communicator of codes for asynchronous data retrieval, which is common to Ajax-based clients, the proposed architecture pattern is able to cut out the graphic design related codes to constitute the View layer. Based on such declarative generalization of complex web-client codes, Ajax-related codes can be easily modularized and efficiently reused in development and maintenance stages, and graphics design can be done separately regardless of the other business logic related codes development, resulting in highly efficient development and maintenance of complex Ajax-based web clients.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1239-1244
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• 2003

In this paper, we analyzed cell loss rate performance for random traffic sources in wireless ATM(Asynchronous Transfer Mode) access architecture, which consists of access node and wireless channel. Applying queueing model to cell level at access node and considering burst error characteristics in wireless channel, we derived a formula about the cell loss rate of the random traffic in the wireless ATM access architecture. We also applied FEC(Forward Error Correction) schemes to improve the cell loss rate of random traffic. When we applied FEC schemes in the wireless ATM access architecture, we confirmed that the concatenated code provides the most superior performance compared to any other codes.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Structural Engineering and Mechanics
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• v.18 no.2
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• pp.231-246
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• 2004

In this paper, a comparison of various random vibration and deterministic dynamic analyses of cable-stayed bridges subjected to asynchronous ground motion is presented. Different random vibration methods are included to determine the dynamic behaviour of a cable-stayed bridge for various ground motion wave velocities. As a numerical example the Jindo Bridge located in South Korea is chosen and a 413 DOF mathematical model is employed for this bridge. The results obtained from a spectral analysis approach are compared with those of two random vibration based response spectrum methods and a deterministic method. The analyses suggest that the structural responses usually show important amplifications depending on the decreasing ground motion wave velocities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2021-2026
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• 2007

In the parer, we design a non-coherent UWB system by adopting the architecture of a simplified asynchronous transmission and the edge-triggered pulse transmission, which makes e system performance independent of the share of the transmitted waveform, robust to multipath channels. The designed non-coherent UWB transceiver architecture has an advantage of the simple realization since any mixer, high-speed correlator, and high-sampling A/D converter are not necessary at the cost of performance degradation of about 3dB. Further, the designed non-coherent UWB transceiver is actually implemented with the wireless CANVAS prototype testbed in short range indoor application environments such as a lecture room. The implemented prototype testbed is proven to offer the data rate of 115kbps on the conditions of Peer-to-Peer(P-to-P) in the indoor channel within the range of about 10m.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.386-393
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• 2017

Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.86-94
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• 2014

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fiber delay line (FDL) buffer. In this article, we propose a method to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for a cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e., the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2891-2898
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• 2014

It is feasible to develop a fault tolerant system through module level redundancy on the Integrated Modular Avionics (IMA). However, its great implementation complexity is one of important challenges when asynchronous hardware environment is naturally assumed. To solve this problem, Physically Asynchronous Logically Synchronous (PALS) on IMA has been proposed. But, it has adaptation problem by not addressing specific architecture for IMA system. In the paper, we propose how to synchronize the input data on the IMA system under primary/secondary redundancy architecture by referring to existing PALS. In the proposed scheme, we introduce window frame by considering rate monotonic scheduling and analyze the adequate the synchronization time. Finally, we verify the feasibility of the proposed design pattern through the systematic experiments.