• The KIPS Transactions:PartD
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• v.13D no.4 s.107
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• pp.593-602
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• 2006

Software development methodology has been developed for satisfying goals of improvement in productivity and reduction in time-to-market through the reuse of software assets. The current methods that implement software product-line, one of software development methodologies, interfere massively with the core assets, which require high cost in assembly level reducing the effectiveness. In this paper, we introduce Aspect-Oriented Programming (AOP) as a method for improving assembly process in software product-line. The method that assembles core assets and variabilities is described by grammar elements such as Join point, pointcut and advice without code-change. We analyze requirements of a mini-system as an example adapting AOP and design using UML. Our study implements the variabilities, which are from design stage, using an Aspect-Oriented Programming Language, AspectJ and prove usability and practicality by implementing the proposed idea using an Aspect-Oriented Programming Language, AspectJ.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.356-365
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• 2002

Test systems verify and classify the various kinds of semiconductor products. So test systems need programs that can test the various special functions of hardware modules and products. Programs can be modified, compiled and executed by engineers. Consequently, the systems needs programming languages that can be easily programmed by engineers and their compilers that can compile and execute teat programs. In this paper we discuss the environment of programming languages and their compilers for the existing domestic teat systems. We design a programming language and implement its compiler that can be conveniently used by the experienced engineers in the industry field. Experimental results show that a newly designed test system with our programming language and compiler can teat products faster than the existing test system.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1649-1657
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• 2005

In this paper, a fast implementation of JPEG is discussed and its application to multimedia service is presented for mobile wireless internet. A fast JPEG player is developed based on several fast algorithms for mobile handset. In the color transformation, RCT is adopted instead of ICT for JPEG source. For the most time-consuming DCT part, the binDCT can reduce the decoding time. In upsampling and RGB conversion, the transformation from YCbCr to RGB 16 bit is made at one time. In some parts, assembly language is applied for high-speed. Also, an implementation of multimedia in mobile handset is described using MJPEG (Motion JPEG) and QCELP(Qualcomm Code Excited Linear Prediction Coding). MJPEG and QCELP are used for video and sound, which are synchronized in handset. For the play of MJPEG, the decoder is implemented as a S/W upon the MSM 5500 baseband chip using the fast JPEG decoder. For the play of QCELP, the embedded QCELP player in handset is used. The implemented multimedia player has a fast speed preserving the image quality.

• Nuclear Engineering and Technology
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• v.54 no.11
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• pp.4226-4230
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• 2022

The Korea Atomic Energy Research Institute (KAERI) has designed a Hybrid-Low Power Research Reactor (H-LPRR) which can be used for critical assembly and conventional research reactor as well. It is an open tank-in-pool type research reactor (Thermal Power: 50 kW_th) of which the most important applications are Neutron Activation Analysis (NAA), Radioisotope (RI) production, education and training. There are eight irradiation holes on the edge of the reactor core: IR (6 holes for RI production) and NA (2 holes for NAA) holes. In order to quantify the elemental concentration in target samples through the Instrumental Neutron Activation Analysis (INAA), it is necessary to measure neutron spectrum parameters such as thermal neutron flux, the deviation from the ideal 1/E epithermal neutron flux distribution (α), and the thermal-to-epithermal neutron flux ratio (f) for the irradiation holes. In this study, the MCNP6.1 code and FORTRAN 90 language are applied to determine the parameters for the two irradiation holes (NA-SW and NA-NW) in H-LPRR, and in particular its α and f parameters are compared to values of other research reactors. The results confirmed that the neutron irradiation holes in H-LPRR are designed to be sufficiently applied to neutron activation analysis, and its performance is comparable to that of foreign research reactors including the TRIGA MARK II.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.37-44
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• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.

• Nuclear Engineering and Technology
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• v.26 no.4
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• pp.502-506
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• 1994

The design of safety computer system is described along with the case of software design and testing in the Core Protection Calculator System (CPCS). The application of computer system in safety system requires not only hardware qualification but thorough testing on software to verify its correctness and completeness. The testing on software for CPCS is performed by comparing the outputs of two versions of code. One is implemented in assembly language and the other is in Fortran. The testing is performed in sequencial and overlapping manner. Phase I test verifies that each software module is implemented correctly by executing every branch. Phase II test verifies that the integrated software is complete, meeting its requirements specification and also the integrated system meet its requirement and timing constraints. Through these testing, the Yonggwang Nuclear Power Plant Units (YGN) 3 and 4 CPCS software is verified to be correct and complete, and the integrated system is designed as in its requirements specification.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.304-315
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• 2001

In this paper, we peformed the real-time implementation of AMR(Adaptive Multi-Rate) speech coding algorithm which is adopted for IMT-2000 service using TMS320C6201, i.e., a Texas Instrument´s fixed-point DSP. With the ANSI C source code released from ETSI, optimization is performed to make it run in real-time with memory as small as possible using the C compiler and assembly language. Implemented AMR speech codec has the size of 32.06 kWords program memory, 9.75 kWords data RAM memory, and 19.89 kWords data ROM memory. And, The time required for processing one frame of 20 ms length speech data is about 4.38 ms, and it is short enough for real-time operation. It is verified that the decoded result of the implemented speech codec on the DSP is identical with the PC simulation result using ANSI C code for test sequences. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.