• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.4
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• pp.876-884
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• 2014

A hardware design of LDPC decoder which is based on the improved normalized min-sum(INMS) decoding algorithm is described in this paper. The designed LDPC decoder supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. The decoding function unit(DFU) which is a main arithmetic block is implemented using sign-magnitude(SM) arithmetic and INMS decoding algorithm to optimize hardware complexity and decoding performance. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 100 MHz clock has 284,409 gates and RAM of 62,976 bits, and it is verified by FPGA implementation. The estimated performance depending on code rate and block length is about 82~218 Mbps at 100 MHz@1.8V.

• Journal of IKEEE
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• v.25 no.3
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• pp.485-492
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• 2021

In this paper, we propose the development of a defect inspection system for polygonal containers. Embedded board consists of main part, communication part, input/output part, etc. The main unit is a main arithmetic unit, and the operating system that drives the embedded board is ported to control input/output for external communication, sensors and control. The input/output unit converts the electrical signals of the sensors installed in the field into digital and transmits them to the main module and plays the role of controlling the external stepper motor. The communication unit performs a role of setting an image capturing camera trigger and driving setting of the control device. The input/output unit converts the electrical signals of the control switches and sensors into digital and transmits them to the main module. In the input circuit for receiving the pulse input related to the operation mode, etc., a photocoupler is designed for each input port in order to minimize the interference of external noise. In order to objectively evaluate the accuracy of the development of the proposed polygonal container defect inspection system, comparison with other machine vision inspection systems is required, but it is impossible because there is currently no machine vision inspection system for polygonal containers. Therefore, by measuring the operation timing with an oscilloscope, it was confirmed that waveforms such as Test Time, One Angle Pulse Value, One Pulse Time, Camera Trigger Pulse, and BLU brightness control were accurately output.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• The Mathematical Education
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• v.57 no.2
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• pp.93-110
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• 2018

One of the biggest changes in the 2015 revised mathematics curriculum is shifting to the second year of middle school in Pythagorean theorem. In this study, the following subjects were studied. First, Pythagoras theorem analyzed the expected problems caused by the shift to the second year middle school. Secondly, we have researched the reconstruction method to solve these problems. The results of this study are as follows. First, there are many different ways to deal with Pythagorean theorem in many countries around the world. In most countries, it was dealt with in 7th grade, but Japan was dealing with 9th grade, and the United States was dealing with 7th, 8th and 9th grade. Second, we derived meaningful implications for the curriculum of Korea from various cases of various countries. The first implication is that the Pythagorean theorem is a content element that can be learned anywhere in the 7th, 8th, and 9th grade. Second, there is one prerequisite before learning Pythagorean theorem, which is learning about the square root. Third, the square roots must be learned before learning Pythagorean theorem. Optimal positions are to be placed in the eighth grade 'rational and cyclic minority' unit. Third, Pythagorean theorem itself is important, but its use is more important. The achievement criteria for the use of Pythagorean theorem should not be erased. In the 9th grade 'Numbers and Calculations' unit, after learning arithmetic calculations including square roots, we propose to reconstruct the square root and the utilization subfields of Pythagorean theorem.

• Spatial Information Research
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• v.17 no.3
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• pp.371-379
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• 2009

Recently, GPU (Graphics Processing Unit) has been improved rapidly on the need of speed for gaming. As a result, GPU contains multiple ALU (Arithmetic Logic Unit) for parallel processing of a lot of graphics data, such as transform, ray tracing, etc. Therefore, this paper proposed a technique for parallel processing of spatial data using GPU. Spatial data consists of multiple coordinates, and each coordinate contains value of x and y axis. To display spatial data graphics operations have to be processed to large amount of coordinates. Because the graphics operation is identical and coordinates are multiple data, SIMD (Single Instruction Multiple Data) parallel processing of GPU can be used for processing of spatial data to improve performance. This paper implemented SIMD parallel processing of spatial data using two kinds of SDK (Software Development Kit). CUDA and ATI Stream are used for NVIDIA and ATI GPU respectively. Experiments that measure time of calculation for graphics operations are carried out to observe enhancement of performance. Experimental result is reported that proposed method can enhance performance up to 1,162% for graphics operations. The proposed method that uses parallel processing with GPU for spatial data can be generally used to enhance performance for applications which deal with large amount of spatial data.

• Communications of Mathematical Education
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• v.33 no.3
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• pp.255-273
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• 2019

In order to help students to understand the essence of prime concepts, this study looked at the history of prime concept development and analyzed how to introduce the concept of textbooks. In ancient Greece, primes were multiplicative atoms. At that time, the unit was not a number, but the development of decimal representations led to the integration of the unit into the number, which raised the issue of primality of 1. Based on the uniqueness of factorization into prime factor, 1 was excluded from the prime, and after that, the concept of prime of the atomic context and the irreducible concept of the divisor context are established. The history of the development of prime concepts clearly reveals that the fact that prime is the multiplicative atom is the essence of the concept. As a result of analyzing the textbooks, the textbook has problems of not introducing the concept essence by introducing the concept of prime into a shaped perspectives or using game, and the problem that the transition to analytic concept definition is radical after the introduction of the concept. Based on the results of the analysis, we have provided several pedagogical implications for helping to focus on a conceptual aspect of prime number.

• Progress in Superconductivity
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• v.4 no.2
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.