• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of Mechanical Science and Technology
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• v.16 no.7
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• pp.959-965
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• 2002

Effective hydraulic conductivity of a statistically anisotropic heterogeneous medium is obtained for steady two-dimensional flows employing stochastic analysis. Flow equations are solved up to second order and the effective conductivity is obtained in a semi-analytic form depending only on the spatial correlation function and the anisotropy ratio of the hydraulic conductivity field, hence becoming a true intrinsic property independent of the flow field. Results are obtained using a statistically anisotropic Gaussian correlation function where the anisotropy is defined as the ratio of integral scales normal and parallel to the mean flow direction. Second order results indicate that the effective conductivity of an anisotropic medium is greater than that of an isotropic one when the anisotropy ratio is less than one and vice versa. It is also found that the effective conductivity has upper and lower bounds of the arithmetic and the harmonic mean conductivities.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.653-662
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• 1989

Cerebellar Model Arithmetic Controller (CMAC) has been introduced as an adaptive control function generator. CMAC computes control functions referring to a distributed memory table storing functional values rather than by solving equations analytically or numerically. CMAC has a unique mapping structure as a coarse coding and supervisory delta-rule learning property. In this paper, learning aspects and a convergence of the CMAC were investigated. The efficient training algorithms were developed to overcome the limitations caused by the conventional maximum error correction training and to eliminate the accumulated learning error caused by a sequential node training. A nonlinear function generator and a motion generator for a two d.o.f. manipulator were simulated. The efficiency of the various learning algorithms was demonstrated through the cpu time used and the convergence of the rms and maximum errors accumulated during a learning process. A generalization property and a learning effect due to the various gains were simulated. A uniform quantizing method was applied to cope with various ranges of input variables efficiently.

• 한국기계연구소 소보
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• s.19
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• pp.93-115
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• 1989

Cerebellar Model Arithmetic Controller(CMAC) has been introduced as an adaptive control function generator. CMAC computes control functions referring to a distributed memory table storing functional values rather than by solving equations analytically or numerically. CMAC has a unique mapping structure as a coarse coding and supervisory delta-rule learning property. In this paper, learning aspects and a convergence of the CMAC were investigated. The efficient training algorithms were developed to overcome the limitations caused by the conventional maximum error correction training and to eliminate the accumulated learning error caused by a sequential node training. A nonlinear function generator and a motion generator for a two d. o. f. manipulator were simulated. The efficiency of the various learning algorithms was demonstrated through the cpu time used and the convergence of the rms and maximum errors accumulated during a learning process; A generalization property and a learning effect due to the various gains were simulated. A uniform quantizing method was applied to cope with various ranges of input variables efficiently.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.10
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• pp.879-885
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• 2013

By performing interval analysis on the system transfer function, we propose an improved method of control loop design for a DC/DC converter. In conventional design methods, the effect of system parameter change due to the specified range of operating conditions and production tolerances in power components should be checked a posteriori, because this may result in a transfer function shift and performance degradation. In the proposed method, a possible parameter change is considered a priori in the design step in order that the desired crossover frequency and sufficient phase margin can be achieved even in the worst case condition. As an illustrative example, a buck dc/dc converter is designed by two different methods and performance comparisons are performed to verify the feasibility of the proposed scheme.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• Journal of the Korean Mathematical Society
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• v.56 no.6
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• pp.1599-1611
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• 2019

Let $m,n{\in}{\mathbb{N}}$. We represent the additive subgroups of the ring ${\mathbb{Z}}_m{\times}{\mathbb{Z}}_n$, which are also (unital) subrings, and deduce explicit formulas for $N^{(s)}(m,n)$ and $N^{(us)}(m,n)$, denoting the number of subrings of the ring ${\mathbb{Z}}_m{\times}{\mathbb{Z}}_n$ and its unital subrings, respectively. We show that the functions $(m,n){\mapsto}N^{u,s}(m,n)$ and $(m,n){\mapsto}N^{(us)}(m,n)$ are multiplicative, viewed as functions of two variables, and their Dirichlet series can be expressed in terms of the Riemann zeta function. We also establish an asymptotic formula for the sum $\sum_{m,n{\leq}x}N^{(s)}(m,n)$, the error term of which is closely related to the Dirichlet divisor problem.

• Journal of the Chungcheong Mathematical Society
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• v.37 no.2
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• pp.57-66
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• 2024

In this paper, we study how the Hilbert polynomial, associated with a reduced closed subscheme X of codimension 2 in ℙ^N, reveals geometric information about X. Although it is known that the Hilbert polynomial can tell us about the scheme's degree and arithmetic genus, we find additional geometric information it can provide for smooth varieties of codimension 2. To do this, we introduce the concept of Gotzmann coefficients, which helps to extract more information from the Hilbert polynomial. These coefficients are based on the binomial expansion of values of the Hilbert function. Our method involves combining techniques from initial ideals and partial elimination ideals in a novel way. We show how these coefficients can determine the degree of certain geometric features, such as the singular locus appearing in a generic projection, for smooth varieties of codimension 2.