• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.464-467
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• 2000

In this paper we introduce the network based multi-motors control system using CAN(Controller Area Network) The traditional multi-motors control system has many problems in the view of reliability and economy because of the amount and complexity of wiring noise and maintenance problems etc, These problems are serious especially when the motor controllers are separated widely CAN is generally applied in car networking in order to reduce the complexity of the related wiring harnesses. These traditional CAN application techniques are modified to achieve the real time communication for the multi-motor control system. And also the position synchronization technique is developed and the proposed methods are verified experimentally.

• 한국정보처리학회논문지
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• 제2권3호
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• pp.433-442
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• 1995

시간 복잡도가 O(Ν)인 고집적 회로(VLSI)의 병렬 정렬기 설계에 관한 논문이다. 발표된 빠른 VLSI 정렬 알고리즘은 Ν개의 데이타를 정렬하기 위해 O(log Ν)시간 복 잡도를 가지고 있다. 그러나 이러한 알고리즘은 입출력 시간을 고려하지 않고, 복잡 한 네트워크 구조를 가지므로 확장이나 실용화하기 힘들다. 입출력 시간이 포함된 병 렬 정렬 알고리즘들의 칩면적과 시간 복잡도를 분석한 후 가장 효과적인 rebound sort 이론을 확장하여 VLSI로 구현한다. 이 리바운드 정렬기는 파이프라인으로 구성하여 O(Ν)의 시간 복잡도를 가지며 한 개의 칩에 8개의 16비트 레코드를 정렬할 수 있다. 그리고 이 정렬 칩은 확장성을 가지고 있어 수직으로 연결할 경우 8개 이상의 레코드 를 정렬할 수 있다.

• 한국정보통신학회논문지
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• 제19권2호
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• pp.450-454
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• 2015

본 논문에서는 평면상에 가중치를 가진 점들이 주어질 때, 임의의 상수 r에 대해서 변의 길이 r인 정사각형 영역을 고려해서 이 안에 속하는 점들의 가중치 합이 최대가 되는 영역을 찾고자 한다. 변의 길이가 정해져 있지 않은 경우에 임의의 사각형 영역을 찾는 문제에 대한 연구가 있었다. 본 논문에서는 상수 r이 주어질 때, 변의 길이 r인 정사각형 영역을 찾는 문제를 다룬다. 우리는 동적 환경 하에서의 일차원 문제를 풀고, 이를 이용해서 O(nlogn+rn) 시간 복잡도를 갖는 알고리즘을 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.34-34
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• 2000

One of the basic goals, when considering networks for communication in industrial control applications, is the reduction of complexity of related wiring harnesses. In addition, the networking offers the advantages for industrial control applications, such as ease of cabling, ease of changes in the cabling, ease of adding controller modules, etc. CAN (Controller Area Network) is generally applied in car networking in order to reduce the complexity of the related wiring harnesses. These traditional CAN application techniques are modified to achieve the real time communication for the industrial control applications. In this paper, we propose the method of CAN Identifier assignment for Real-Time network system. This method is can be used to scheduling messages on CAN for Real-Time network system. And also, the real-time network system is developed and the proposed moth(Ids are verified experimentally.

• 전자공학회논문지A
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• 제32A권5호
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• 대한임베디드공학회논문지
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• 제12권1호
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권5호
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• pp.1733-1751
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• 2015

The IEEE 802.15.4 standard not only provides a maximum of seven guaranteed time slots (GTSs) for allocation within a superframe to support time-critical traffic, but also achieves ultralow complexity, cost, and power in low-rate and short-distance wireless personal area networks (WPANs). Real-time wireless body area sensor networks (WBASNs), as a special purpose WPAN, can perfectly use the IEEE 802. 15. 4 standard for its wireless connection. In this paper, we propose an adaptive GTS allocation scheme for real-time WBASN data transmissions with different priorities in consideration of low latency, fairness, and bandwidth utilization. The proposed GTS allocation scheme combines a weight-based priority assignment algorithm with an innovative starvation avoidance scheme. Simulation results show that the proposed method significantly outperforms the existing GTS implementation for the traditional IEEE 802.15.4 in terms of average delay, contention free period bandwidth utilization, and fairness.

• 한국통신학회논문지
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• 제29권8C호
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• pp.1047-1054
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• 2004

본 논문에서는 AOP(All One Polynomial)에 의해 결정되는 유한체 GF(2$^{m}$ )상의 곱셈을 위한 두 가지 종류의 시스톨릭 어레이를 제안한다. 제안된 두 시스톨릭 어레이 모두 패러럴 입출력 구조를 가진다. 첫 번째 제안된 곱셈기는 O($m^2$)의 면적 복잡도와 O(1)의 시간 복잡도를 가진다. 다시 말하면, 이 곱셈기는 m(m+1)/2 개의 동일한 셀들로 이루어지며 초기 m/2+1 사이클 지연 후, 1 사이클마다 곱셈의 결과를 출력한다. 첫 번째 제안된 곱셈기를 기존의 AOP를 사용하는 병렬형 시스톨릭 곱셈기와 비교 분석한 결과 하드웨어 및 계산지연 시간에 있어 각각 12% 및 50%의 성능 개선을 보인다. 두 번째 제안된 시스톨릭 곱셈기는 암호응용을 위해 선형 어레이로 설계되었으며, O(m)의 면적 복잡도와 O(m)의 시간 복잡도를 가진다. 즉, m+1 개의 동일한 셀들로 이루어지며 m/2+1 사이클마다 곱셈의 결과를 출력한다. 두 번째 곱셈기를 기존의 선형 시스톨릭 곱셈기들과 비교 분석한 결과, 하드웨어, 계산지연 시간, 그리고 처리율에 있어 각각 43%, 83%, 그리고 50%의 성능 개선을 보인다. 또한 제안된 곱셈기들은 높은 규칙성과 모듈성을 가지기 때문에 VLSI 구현에 매우 적합하다. 따라서 GF(2$^{m}$ ) 응용을 위해, 본 연구에서 제안된 곱셈기들을 사용하면 최소의 하드웨어 사용으로 최대의 성능을 얻을 수 있다.

• 대한임베디드공학회논문지
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• 제13권1호
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• pp.1-8
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• 2018

This paper proposes a low complexity super resolution algorithm for frequency modulated continuous wave (FMCW) radar systems for foreign object debris (FOD) detection. FOD radar has a requirement to detect foreign object in small units in a large area. However, The fast Fourier transform (FFT) method, which is most widely used in FMCW radar, has a disadvantage in that it can not distinguish between adjacent targets. Super resolution algorithms have a significantly higher resolution compared with the detection algorithm based on FFT. However, in the case of the large number of samples, the computational complexity of the super resolution algorithms is drastically high and thus super resolution algorithms are difficult to apply to real time systems. In order to overcome this disadvantage of super resolution algorithm, first, the proposed algorithm coarsely obtains the frequency of the beat signal by employing FFT. Instead of using all the samples of the beat signal, the number of samples is adjusted according to the frequency of the beat signal. By doing so, the proposed algorithm significantly reduces the computational complexity of multiple signal classifier (MUSIC) algorithm. Simulation results show that the proposed method achieves accurate location even though it has considerably lower complexity than the conventional super resolution algorithms.