• Proceedings of the KIEE Conference
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.473-475
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• 2001

This paper proposed a MPPT ( Maximum Power Point Tracking) control algorithm for PV(Photovoltaic) array based on a modified constant voltage control MPPT algorithm at low-insolation. This method which combines a IncCond(Incremental Conductance) and a constant voltage control algorithm. In contrast to the typical conventional MPPT algorithm, the proposed method have been obtained high efficiency and good performance. The proposed algorithm is verified through simulation result. In order to confirm the availability of the scheme, a simulation used PSIM and ACSL software tool.

• Journal of Sensor Science and Technology
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• 제18권5호
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• pp.372-376
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• 2009

This paper describes the characteristics of piezoelectric micro power generators by the ANSYS FEA(finite element analysis). The micro power generator was designed to convert ambient vibration energy to electrical power as a ZnO piezoelectric material. To find optimal model in low vibration ambient, the shape of power generator was changed with different membrane width, thickness, length, and proof mass size. Using the ANSYS modal analysis, bending mode and stress distribution of optimal model were analyzed. Moreover, the displacement with the frequency range was analyzed by harmonic analysis. From the simulation results, the resonance frequency of optimal model is about 373 Hz and investigate the possibility of ZnO micro power generator for ambient vibration applications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권1호
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• pp.1-10
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• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.523-524
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• 2008

Proposed battery charger is a economic candidate because that is simple and small size. The circuit has linearly operational power stage. That use small size buffer with small driving current and large power MOS gate capacitance. The simulation result show that charging current is stable and has low ripple.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권11호
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• pp.5381-5399
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• 2016

Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.286-292
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• 2006

This paper presents the design of a low-voltage wide-band switched-capacitor (SC) filter for wireless communication receiver applications. The filter is the 5th-order Elliptic lowpass filter. With the clock frequency of 50MHz implying that an effective sampling frequency is 100MHz with double sampling scheme, the cut-off frequency of the filter is programmable to be 1.25MHz, 2.5MHz, 5MHz and 10MHz. For low-power systems powered by a single-cell battery, the SC filter was elaborately designed to operate at 1.2V power supply. Simulation result shows that the 3rd-order input intercept point (IIP3) can be up to 27dBm. The filter was fabricated in a $0.25-{\mu}m$ 1P5M standard CMOS technology and measured frequency responses show good agreement with the simulation ones. The current consumption is 34mA at a 1.2V power supply.

• Proceedings of the KIPE Conference
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• 전력전자학회 1997년도 전력전자학술대회 논문집
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• pp.239-242
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• 1997

In this paper, the new filter that reduced output ripple to zero is proposed. This filter is composed of transformer and capacitor. The operating mode is verified with theoretical analysis of low ripple filter and computer simulation. DC-DC converter of input voltage DC 100[V], output 30[V]/30[A], switching frequency 20[KHz] is manufactured. In the result, computer simulation analysis is same to experimental result.

• Proceedings of the KIPE Conference
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.421-424
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• 2000

Direct Torque Control(DTC) of AC motor has the fast torque and flux dynamic responses even though it has very simple scheme to implement. However DTC do not show good performance at low speed range with conventional open loop stator flux observer when stator resistance varied. So authors proposed nonlinear stator flux obsever in order to flux estimation at low speed and show its simulation results.

• ETRI Journal
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• 제32권4호
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• Proceedings of the KIEE Conference
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1333-1335
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• 2005

STATCOM has many advantages rather tan SVC at a view point of a continuous controllability of reactive power and response time of reactive power compensation In this paper, 30kVA STATCOM for compensation of low voltage industrial loads is designed and its operation characteristics is analyzed and verified by simulation.