• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.38-49
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• 1998

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed for real-time or high-speed(faster than real-time) simulators. This paper presents an enhanced strategy in which high computing power can be provided by parallel processing of DSP processors with communication links. DSP system is designed for general purpose. Parallel DSP system can be easily expanded by just connecting new DSP modules to the system. General urpose DSP modules and a VME interface module was developed. New model and techniques for the task allocation are also presented which take into account the special characteristics of parallel I/O and computation. As a realistic cost function of task allocation, we suggested 'simulation period' which represents the period of simulation output intervals. Based on the development of parallel DSP system and realistic task allocation techniques, we cound achieve good efficiency of parallel processing and faster simulation speed than real-time.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.24-37
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• 2024

To address the requirement for high-speed encryption of large amounts of data, this study improves the widely adopted cipher block chaining (CBC) mode and proposes a controllable parallel cipher block chaining (CPCBC) block cipher mode of operation. The mode consists of two phases: extension and parallel encryption. In the extension phase, the degree of parallelism n is determined as needed. In the parallel encryption phase, n cipher blocks generated in the expansion phase are used as the initialization vectors to open n parallel encryption chains for parallel encryption. The security analysis demonstrates that CPCBC mode can enhance the resistance to byte-flipping attacks and padding oracle attacks if parallelism n is kept secret. Security has been improved when compared to the traditional CBC mode. Performance analysis reveals that this scheme has an almost linear acceleration ratio in the case of encrypting a large amount of data. Compared with the conventional CBC mode, the encryption speed is significantly faster.

• Journal of Korean Institute of Industrial Engineers
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• v.19 no.4
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• pp.125-135
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• 1993

An Unrelated Parallel Processing with Weighted jobs and Setup times scheduling prolem is studied. We consider a parallel processing in which a group of processors(machines) perform a single operation on jobs of a number of different job types. The processing time of each job depends on both the job and the machine, and each job has a weight. In addition each machine requires significant setup time between processing jobs of different job types. The performance measure is to minimize total weighted flow time in order to meet the job importance and to minimize in-process inventory. We present a 0-1 Mixed Integer Programming model as an optimizing algorithm. We also present a simple heuristic algorithm. Computational results for the optimal and the heuristic algorithm are reported and the results show that the simple heuristic is quite effective and efficient.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.32 no.2
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• pp.85-93
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• 2009

GOMS model is a cognitive modeling method of human performance based on Goal, Operators, Methods, Selection rules. GOMS model was originally designed for desktop environment so that it is difficult for GOMS model to be implemented into the mobile environment. In addition, GOMS model would be inaccurate because the original GOMS model was based on serial processing, excluding one of most important human information processing characteristics, parallel processing. Therefore this study was designed to propose a modified GOMS model including mobile computing and parallel processing. In order to encompass mobile environment, an operator of 'look for' was divided into 'visual move to' and 'recognize' whereas 'point to' and 'click' were combined into 'tab.' The results showed that newly introduced operators were necessary to estimate more accurate mobile computing behaviors. In conclusion, modified-GOMS model could predict human performance more accurately than the original GOMS model in the mobile computing environment.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• Journal of Mechanical Science and Technology
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• v.18 no.7
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• pp.1121-1130
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• 2004

The Genetic Algorithm (GA), an optimization technique based on the theory of natural selection, has proven to be a relatively robust means of searching for global optimum. It converges to the global optimum point without auxiliary information such as differentiation of function. In the case of a complex problem, the GA involves a large population number and requires a lot of computing time. To improve the process, this research used parallel processing with several personal computers. Parallel process technique is classified into two methods according to subpopulation's size and number. One is the fine-grained method (FGM), and the other is the coarse-grained method (CGM). This study selected the CGM as a parallel process technique because the load is equally divided among several computers. The given design domain should be reduced according to the degree of feasibility, because mechanical system problems have constraints. The reduced domain is used as an initial design domain. It is consistent with the feasible domain and the infeasible domain around feasible domain boundary. This parallel process used the Message Passing Interface library.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.755-765
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• 2004

Recently, the Internet-based distributed/parallel computing using many of idle hosts has been demonstrated its usefulness for processings of a large-scale task and involving several important issues. While executing a large-scale task, the realtime monitoring is required for adaptive strategy of the performance and state change of host. This paper provides the realtime monitoring and visualization on global computing infrastructure called PDP(Parallel Distributed Processing) which is a parallel computing framework implemented with Jana for parallel computing on the Internet.

• Journal of Mechanical Science and Technology
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• v.16 no.5
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• pp.609-618
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• 2002

In practical designs, most of the multidisciplinary problems have a large-size and complicate design system. Since multidisciplinary problems have hundreds of analyses and thousands of variables, the grouping of analyses and the order of the analyses in the group affect the speed of the total design cycle. Therefore, it is very important to reorder and regroup the original design processes in order to minimize the total computational cost by decomposing large multidisciplinary problems into several multidisciplinary analysis subsystems (MDASS) and by processing them in parallel. In this study, a new decomposition method is proposed for parallel processing of multidisciplinary design optimization, such as collaborative optimization (CO) and individual discipline feasible (IDF) method. Numerical results for two example problems are presented to show the feasibility of the proposed method.