• Explosives and Blasting
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• v.28 no.2
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• pp.1-16
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• 2010

This study focuses on the phenomenon that the blast damaged zone developed on rock slope surfaces can be affected by joint characteristics rather than by explosive power when the pre-splitting is applied to excavate a jointed rock slope. The characteristics of rock joints on a slope were investigated and categorized them into 4 cases. Also an image processing system has been used for comparing the distribution pattern of rock blocks. From this investigation, it was found that the rock blocks bigger than 2,000 mm occupied 42% in the case of single joint set and it showed the well efficiency of pre-splitting blast. In cases of 2~3 parallel joint sets and 2~3 intersecting joint sets are developed on rock surfaces, the rock blocks in the range of 1,000~2,000 mm occupied 43.6% and 35.8%, respectively, and it showed that the efficiency of pre-splitting was decreased. When more than 3 joint sets are randomly developed, however, the rock blocks in the range of 250~500 mm occupied 35% and there was no block bigger than 1,000 mm. This denotes that the blasting with pre-splitting was not effective. The numerical analysis using PFC2D showed that the blast damaged zone in a rock mass could be directly influenced by the pre-splitting. It is, therefore, required to investigate the discontinuity pattern on rock surfaces in advance, when the pre-splitting method is applied to excavate jointed rock slopes and to apply a flexible blating design with a consideration of the joint characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Geophysics and Geophysical Exploration
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• v.13 no.4
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• pp.307-314
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• 2010

Although conventional seismic data processing is based on the assumption that the media are isotropic, the subsurface is often anisotropy in shale formation or carbonate with cracks and fractures. This paper presents the anisotropic parameter and seismic modeling in transversely isotropic media with a vertical symmetry axis using seismic physical modeling. The experiment was successfully carried out with VTI media, laminated bakelite material, using contact transducer of p and s-wave transmission. The variation of velocities with angle of incidence was clearly shown in anisotropic material. Comparing these velocities with the calculated phase velocities, the (P) and (S)-wave velocity observed in anisotropic material was a very good agreement with the calculated values. Anisotropic parameter ${\varepsilon}$, ${\delta}$, ${\gamma}$ was estimated by using Lame's constant calculated from the observed velocity. For the purpose of testing (S)-wave polarization, a birefringence experiment was carried out. The higher velocity was associated with the polarization parallel to the fracture, and the lower velocity was associated with the polarization perpendicular to the fracture.

• Journal of Digital Contents Society
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• v.11 no.2
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• pp.177-184
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• 2010

These days, as digital producing technique has been developed, 3D imaging technique is used in high-tech computer and T.V. Also study for 3D producing technique is actively in progress. Moreover, as James Cameron's movie, 'Avatar' released in 2009 was a box office hit, the issue about 3D image came to the fore again. At this point, I decided to study the effect of the visual depth caused by the color correction during the post-production stage. The purpose of this study is to offer information about processing effective images through data about the effect of the visual depth that applies the color correction during the post-production stage. Basically, I supposed that color and contract would have effects on depth of 3D image. As a result, I could find out the changes of visual depth, space perception and sense of depth throughout the experiment. Applying this result,, I produced the 15 minutes of 3D advertisement movie and I found out that the color correction during the post-production stage was very effective for 3D depth. The left image and the right image by beam splitter based rig and parallel rig were used for this study. Also I adjusted the strong contrast by the color correction during the post-production stage after correcting convergence and visual depth during editing. As a result, I could produce images which had strong sense of space and sense of depth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• Journal of KIISE:Databases
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• v.29 no.3
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• pp.180-192
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• 2002

We investigate the effect of the data skew of join attributes on the performance of a pipelined multi-way hash join method, and propose two new harsh join methods in the shared-nothing multiprocessor environment. The first proposed method allocates buckets statically by round-robin fashion, and the second one allocates buckets dynamically via a frequency distribution. Using harsh-based joins, multiple joins can be pipelined to that the early results from a join, before the whole join is completed, are sent to the next join processing without staying in disks. Shared nothing multiprocessor architecture is known to be more scalable to support very large databases. However, this hardware structure is very sensitive to the data skew. Unless the pipelining execution of multiple hash joins includes some dynamic load balancing mechanism, the skew effect can severely deteriorate the system performance. In this parer, we derive an execution model of the pipeline segment and a cost model, and develop a simulator for the study. As shown by our simulation with a wide range of parameters, join selectivities and sizes of relations deteriorate the system performance as the degree of data skew is larger. But the proposed method using a large number of buckets and a tuning technique can offer substantial robustness against a wide range of skew conditions.