• Title/Summary/Keyword: and Parallel Processing

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NoSQL-based Sensor Web System for Fine Particles Analysis Services (미세먼지 분석 서비스를 위한 NoSQL 기반 센서 웹 시스템)

  • Kim, Jeong-Joon;Kwak, Kwang-Jin;Park, Jeong-Min
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.2
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    • pp.119-125
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    • 2019
  • Recently, it has become a social problem due to fine particles. There are more people wearing masks, weather alerts and disaster notices. Research and policy are actively underway. Meteorologically, the biggest damage caused by fine particles is the inversion layer phenomenon. In this study, we designed a system to warn fine Particles by analyzing inversion layer and wind direction. This weather information system proposes a system that can efficiently perform scalability and parallel processing by using OGC sensor web enablement system and NoSQL storage for sensor control and data exchange.

Fundamental Function Design of Real-Time Unmanned Monitoring System Applying YOLOv5s on NVIDIA TX2TM AI Edge Computing Platform

  • LEE, SI HYUN
    • International journal of advanced smart convergence
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    • v.11 no.2
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    • pp.22-29
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    • 2022
  • In this paper, for the purpose of designing an real-time unmanned monitoring system, the YOLOv5s (small) object detection model was applied on the NVIDIA TX2TM AI (Artificial Intelligence) edge computing platform in order to design the fundamental function of an unmanned monitoring system that can detect objects in real time. YOLOv5s was applied to the our real-time unmanned monitoring system based on the performance evaluation of object detection algorithms (for example, R-CNN, SSD, RetinaNet, and YOLOv5). In addition, the performance of the four YOLOv5 models (small, medium, large, and xlarge) was compared and evaluated. Furthermore, based on these results, the YOLOv5s model suitable for the design purpose of this paper was ported to the NVIDIA TX2TM AI edge computing system and it was confirmed that it operates normally. The real-time unmanned monitoring system designed as a result of the research can be applied to various application fields such as an security or monitoring system. Future research is to apply NMS (Non-Maximum Suppression) modification, model reconstruction, and parallel processing programming techniques using CUDA (Compute Unified Device Architecture) for the improvement of object detection speed and performance.

Robust seismic retrofit design framework for asymmetric soft-first story structures considering uncertainties

  • Assefa Jonathan Dereje;Jinkoo Kim
    • Structural Engineering and Mechanics
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    • v.86 no.2
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    • pp.249-260
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    • 2023
  • The uncertainties involved in structural performances are of importance when the optimum number and property of seismic retrofit devices are determined. This paper proposes a seismic retrofit design framework for asymmetric soft-first-story buildings, considering uncertainties in the soil condition and seismic retrofit device. The effect of the uncertain parameters on the structural performance is used to find a robust and optimal seismic retrofit solution. The framework finds a robust and optimal seismic retrofit solution by finding the optimal locations and mechanical properties of the seismic retrofit device for different realizations of the uncertain parameters. The structural performance for each realization is computed to evaluate the effect of the uncertainty parameters on the seismic performance. The framework utilizes parallel processing to decrease the computationally intensive nonlinear dynamic analysis time. The framework returns a robust design solution that satisfies the given limit state for every realization of the uncertain parameters. The proposed framework is applied to the seismic retrofit design of a five-story asymmetric soft-first-story case study structure retrofitted with a viscoelastic damper. Robust optimal parameters for retrofitting a structure to satisfy the limit state for the different realizations of the uncertain parameter are found using the proposed framework. According to the performance evaluation results of the retrofitted structure, the developed framework is proved effective in the seismic retrofit of the asymmetric structure with inherent uncertainties.

A Study on Machine Learning Compiler and Modulo Scheduler (머신러닝 컴파일러와 모듈로 스케쥴러에 관한 연구)

  • Doosan Cho
    • Journal of the Korean Society of Industry Convergence
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    • v.27 no.1
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    • pp.87-95
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    • 2024
  • This study is on modulo scheduling algorithms for multicore processor in machine learning applications. Machine learning algorithms are designed to perform a large amount of operations such as vectors and matrices in order to quickly process large amounts of data stream. To support such large amounts of computations, processor architectures to support applications such as artificial intelligence, neural networks, and machine learning are designed in the form of parallel processing such as multicore. To effectively utilize these multi-core hardware resources, various compiler techniques are being used and studied. In this study, among these compiler techniques, we analyzed the modular scheduler, which is especially important in one core's computation pipeline. This paper looked at and compared the iterative modular scheduler and the swing modular scheduler, which are the most widely used and studied. As a result, both schedulers provided similar performance results, and when measuring register pressure as an indicator, it was confirmed that the swing modulo scheduler provided slightly better performance. In this study, a technique that divides recurrence edge is proposed to improve the minimum initiation interval of the modulo schedulers.

Battle Simulator for Multi-Robot Mission Simulation and Reinforcement Learning (다중로봇 임무모의 및 강화학습을 위한 전투급 시뮬레이터 연구)

  • Jungho Bae;Youngil Lee;Dohyun Kim;Heesoo Kim;Myoungyoung Kim;Myungjun Kim;Heeyoung Kim
    • Journal of the Korea Institute of Military Science and Technology
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    • v.27 no.5
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    • pp.619-627
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    • 2024
  • As AI technology advances, interest in performing multi-robot autonomous missions for manned-unmanned teaming (MUM-T) is increasing. In order to develop autonomous mission performance technology for multiple robots, simulation technology that reflects the characteristics of real robots and can flexibly apply various missions is needed. Additionally, in order to solve complex non-linear tasks, an API must be provided to apply multi-robot reinforcement learning technology, which is currently under active research. In this study, we propose the campaign model to flexibly simulate the missions of multiple robots. We then discuss the results of developing a simulation environment that can be edited and run and provides a reinforcement learning API including acceleration performance. The proposed simulated control module and simulated environment were verified using an enemy infiltration scenario, and parallel processing performance for efficient reinforcement learning was confirmed through experiments.

A New Pitch Detection Method Using The WRLS-VFF-VT Algorithm (WRLS-VFF-VT 알고리듬을 이용한 새로운 피치 검출 방법)

  • Lee, Kyo-Sik;Park, Kyu-Sik
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.10
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    • pp.2725-2736
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    • 1998
  • In this paper. we present a new pitch determination method for speech analysis. namely VFF(Variable Forgetting Factor) based. by using the WRLS-VFF-VT(Weighted Recursive Least Square-Variable Forgetting Factor-Variable Threshold) algorithm. A proposed method uses VFF to identify the glottal closure points which correspond to the instants of the main excitation pulses for voiced speech. The modified EGG

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Efficient Regular Expression Matching Using FPGA (FPGA를 이용한 효율적 정규표현매칭)

  • Lee, Jang-Haeng;Lee, Seong-Won;Park, Neung-Soo
    • The KIPS Transactions:PartC
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    • v.16C no.5
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    • pp.583-588
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    • 2009
  • Network intrusion detection system (NIDS) monitors all incoming packets in the network and detects packets that are malicious to internal system. The NIDS should also have ability to update detection rules because new attack patterns are unpredictable. Incorporating FPGAs into the NIDS is one of the best solutions that can provide both high performance and high flexibility comparing with other approaches such as software solutions. In this paper we propose and design a novel approach, prefix sharing parallel pattern matcher, that can not only minimize additional resources but also maximize the processing performance. Experimental results showed that the throughput for 16-bit input is twice larger than for 8-bit input but the used LEs/Char in FPGA increases only 1.07 times.

A Study on the Data Collection Methods based Hadoop Distributed Environment (하둡 분산 환경 기반의 데이터 수집 기법 연구)

  • Jin, Go-Whan
    • Journal of the Korea Convergence Society
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    • v.7 no.5
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    • pp.1-6
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    • 2016
  • Many studies have been carried out for the development of big data utilization and analysis technology recently. There is a tendency that government agencies and companies to introduce a Hadoop of a processing platform for analyzing big data is increasing gradually. Increased interest with respect to the processing and analysis of these big data collection technology of data has become a major issue in parallel to it. However, study of the collection technology as compared to the study of data analysis techniques, it is insignificant situation. Therefore, in this paper, to build on the Hadoop cluster is a big data analysis platform, through the Apache sqoop, stylized from relational databases, to collect the data. In addition, to provide a sensor through the Apache flume, a system to collect on the basis of the data file of the Web application, the non-structured data such as log files to stream. The collection of data through these convergence would be able to utilize as a basic material of big data analysis.

Decoding Method of LDPC Codes in IEEE 802.16e Standards for Improving the Convergence Speed (IEEE 802.16e 표준에 제시된 LDPC 부호의 수렴 속도 개선을 위한 복호 방법)

  • Jang, Min-Ho;Shin, Beom-Kyu;Park, Woo-Myoung;No, Jong-Seon;Jeon, In-San
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.12C
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    • pp.1143-1149
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    • 2006
  • In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

SHA-1 Pipeline Configuration According to the Maximum Critical Path Delay (최대 임계 지연 크기에 따른 SHA-1 파이프라인 구성)

  • Lee, Je-Hoon;Choi, Gyu-Man
    • Convergence Security Journal
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    • v.16 no.7
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    • pp.113-120
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    • 2016
  • This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.