• Title/Summary/Keyword: and Parallel Processing

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Inhomogeneous bonding state modeling for vibration analysis of explosive clad pipe

  • Cao, Jianbin;Zhang, Zhousuo;Guo, Yanfei;Gong, Teng
    • Steel and Composite Structures
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    • v.31 no.3
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    • pp.233-242
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    • 2019
  • Early detection of damage bonding state such as insufficient bonding strength and interface partial contact defect for the explosive clad pipe is crucial in order to avoid sudden failure and even catastrophic accidents. A generalized and efficient model of the explosive clad pipe can reveal the relationship between bonding state and vibration characteristics, and provide foundations and priory knowledge for bonding state detection by signal processing technique. In this paper, the slender explosive clad pipe is regarded as two parallel elastic beams continuously joined by an elastic layer, and the elastic layer is capable to describe the non-uniform bonding state. By taking the characteristic beam modal functions as the admissible functions, the Rayleigh-Ritz method is employed to derive the dynamic model which enables one to consider inhomogeneous system and any boundary conditions. Then, the proposed model is validated by both numerical results and experiment. Parametric studies are carried out to investigate the effects of bonding strength and the length of partial contact defect on the natural frequency and forced response of the explosive clad pipe. A potential method for identifying the bonding quality of the explosive clad pipe is also discussed in this paper.

Design and implementation of the SliM image processor chip (SliM 이미지 프로세서 칩 설계 및 구현)

  • 옹수환;선우명훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.10
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    • pp.186-194
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    • 1996
  • The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

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Low-Power Block Filtering Architecture for Digital IF Down Sampler and Up Sampler (디지털 IF 다운 샘플러와 업 샘플러의 저전력 블록 필터링 아키텍처)

  • 장영범;김낙명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.5A
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    • pp.743-750
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    • 2000
  • In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

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A Hybrid Mechanism of Particle Swarm Optimization and Differential Evolution Algorithms based on Spark

  • Fan, Debin;Lee, Jaewan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.12
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    • pp.5972-5989
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    • 2019
  • With the onset of the big data age, data is growing exponentially, and the issue of how to optimize large-scale data processing is especially significant. Large-scale global optimization (LSGO) is a research topic with great interest in academia and industry. Spark is a popular cloud computing framework that can cluster large-scale data, and it can effectively support the functions of iterative calculation through resilient distributed datasets (RDD). In this paper, we propose a hybrid mechanism of particle swarm optimization (PSO) and differential evolution (DE) algorithms based on Spark (SparkPSODE). The SparkPSODE algorithm is a parallel algorithm, in which the RDD and island models are employed. The island model is used to divide the global population into several subpopulations, which are applied to reduce the computational time by corresponding to RDD's partitions. To preserve population diversity and avoid premature convergence, the evolutionary strategy of DE is integrated into SparkPSODE. Finally, SparkPSODE is conducted on a set of benchmark problems on LSGO and show that, in comparison with several algorithms, the proposed SparkPSODE algorithm obtains better optimization performance through experimental results.

Property Analysis for Parallel Processing and Hamiltonian Cycles of Hierarchical Cubic Network (계층적 하이퍼큐브의 해밀튼이안 성질과 병렬처리를 위한 성질 분석)

  • 김종석;이형옥;허영남
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.10a
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    • pp.412-418
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    • 2000
  • In this paper, we will propose that HCN(n,n) gets Hamiltonian Cycles and analyze embedding among HCN(n,n) and UFN(n,n), and HFN(n,n) and In-hypercube. Further, we will prove that HCN(n,n) can be embedded into HFN(n,n) with dilation 3 and the cost for HFN(n,n) to be embedded into HCN(n,n) will be O(n), and HW(n,n) can be embedded into 2n-hypercube with dilation 3 and the cost for In-hypercube to be embedded into HFN(n,n) will be O(n).

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Single-Chip Controller Design for Piezoelectric Actuators using FPGA (FPGA를 이용한 압전소자 작동기용 단일칩 제어기 설계)

  • Yoon, Min-Ho;Park, Jungkeun;Kang, Taesam
    • Journal of Institute of Control, Robotics and Systems
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    • v.22 no.7
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    • pp.513-518
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    • 2016
  • The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

Design and Implementation of the 155Mbps Adaptive CODEC for Ka-band Satellite Communications

  • Park, Eun-A;Chang, Dae-Ig;Kim, Nae-Soo
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1940-1943
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    • 2002
  • In this paper, we presented the design and implementation of 155Mbps satellite Modem adaptively compensated against the rain attenuation. In order to compensate the rain attenuation over high-speed satellite ink, the adaptive coding schemes with variable coding rates and the pragmatic TCM that can be decoded both the QPSK and TC-8PSK using same Viterbi decoder was studied and analyzed. The pragmatic TCM with rate 213, selected to the optimal parameters for implementation, was modeled by VHDL in this paper. The key design issues are how to achieve a high data rate and how to integrated into a single ASIC chip various functions such as the different data rates, Scrambler/descrambler, Interleaver, Encoder/decoder, and BPSK/QPSK/8PSK modulator/demodulator. The implemented 155M0ps adaptive MODEM has the simplified interface circuits among the many functional blocks, and parallel processing architecture to achieve the high data rate. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the 0.25 $\mu\textrm{m}$ CMOS standard cell technology.

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Performance of Tilting Pad Journal Bearings with Different Thermal Boundary Conditions (열 경계 조건이 다른 틸팅패드저널베어링의 성능)

  • Suh, Junho;Hwang, Cheolho
    • Tribology and Lubricants
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    • v.37 no.1
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    • pp.14-24
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    • 2021
  • This study shows the effect of the thermal boundary condition around the tilting pad journal bearing on the static and dynamic characteristics of the bearing through a high-precision numerical model. In many cases, it is very difficult to predict or measure the exact thermal boundary conditions around bearings at the operating site of a turbomachine, not even in a laboratory. The purpose of this study is not to predict the thermal boundary conditions around the bearing, but to find out how the performance of the bearing changes under different thermal boundary conditions. Lubricating oil, bearing pads and shafts were modeled in three dimensions using the finite element method, and the heat transfer between these three elements and the resulting thermal deformation were considered. The Generalized Reynolds equation and three-dimensional energy equation that can take into account the viscosity change in the direction of the film thickness are connected and analyzed by the relationship between viscosity and temperature. The numerical model was written in in-house code using MATLAB, and a parallel processing algorithm was used to improve the analysis speed. Constant temperature and convection temperature conditions are used as the thermal boundary conditions. Notably, the conditions around the bearing pad, rather than the temperature boundary conditions around the shaft, have a greater influence on the performance changes of the bearing.

A Study on The Implementation of Stable and High-speed Humanoid Robot (ICCAS 2004)

  • Kim, Seung-Woo;Jung, Yong-Rae;Jang, Kyung-Jun
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.1440-1443
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    • 2004
  • Most previous robots had used the wheels as means for movement. These structures were relatively simple and easy to control and this is why the method had been used until currently. However, there are many realistic problems to move from one place to another in human life, for instance, steps and edges. So we need to develop the two-legged walking humanoid robot. The 2-legged walking Robot system has been vigorously developed in so many corporations and academic circles of several countries. However, 2-legged walking Robot has been mostly studied in view of the static walk. We design a stable humanoid Robot which can walk in high-speed through the research of the dynamic walk in this paper. Especially, worldwide companies have been interested in developing humanoid robots for a long time to solve the before mentioned problems so that they can become more familiar with the human form. The most important thing, for the novel two-legged walk, is to create a stable and fast walking in two-legged robots. For realization of this movement, an optimal mechanical design of 12 DOFS, a distributed control and a parallel processing control are implemented in this paper. This paper proves that high speed and stable walking can be achieved, through experiments.

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A Helicopter-borne Pulse Doppler Radar Signal Processor Development (헬기탑재 펄스 도플러 레이다 신호처리기 개발)

  • Kwag, Young-Kil;Jeun, In-Pyung;Choi, Min-Su;Hwang, Gwang-Yeon;Lee, Kang-Hoon;Lee, Jae-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.443-446
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    • 2005
  • This paper presents the results of the design and implementation of the airborne pulse doppler radar signal processor using high multi-DSP for the multi-function radar capability such as short-range, midium-range, and long-range depending on the mission of the vehicle. Particularly, the radar signal processor is developed using two DSP boards in parallel for the various radar signal processing algorithm. The key algorithms include LFM chirp waveform-based pulse compression, MTI clutter filter, MTD processor, adaptive CFAR, and clutter map. Especially airborne moving clutter Doppler spectrum compensation algorithm such as TACCAR is implemented for the multi-mode airborne radar system. The test results shows the good Doppler spectral separation for the clutter and the moving target in the flight test environment using helicopter

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