• Title/Summary/Keyword: and Parallel Processing

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Front-End Design for Underwater Communication System with 25 kHz Carrier Frequency and 5 kHz Symbol Rate (25kHz 반송파와 5kHz 심볼율을 갖는 수중통신 수신기용 전단부 설계)

  • Kim, Seung-Geun;Yun, Chang-Ho;Park, Jin-Young;Kim, Sea-Moon;Park, Jong-Won;Lim, Young-Kon
    • Journal of Ocean Engineering and Technology
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    • v.24 no.1
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    • pp.166-171
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    • 2010
  • In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

Design of an Efficient VLSI Architecture and Verification using FPGA-implementation for HMM(Hidden Markov Model)-based Robust and Real-time Lip Reading (HMM(Hidden Markov Model) 기반의 견고한 실시간 립리딩을 위한 효율적인 VLSI 구조 설계 및 FPGA 구현을 이용한 검증)

  • Lee Chi-Geun;Kim Myung-Hun;Lee Sang-Seol;Jung Sung-Tae
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.2 s.40
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    • pp.159-167
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    • 2006
  • Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

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Parallel $XY{\theta}$ Table Design and Implementation for Precision Positioning (고정밀 위치 제어용 병렬 $XY{\theta}$ 테이블 설계 및 구현)

  • Han, Joo-Hun;Oh, Choon-Suk;Ryu, Young-Kee
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.7
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    • pp.62-70
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    • 1999
  • To achieve precision positioning, working area is required within $5mm{\times}5mm$ and positioning error is allowed within minimum ${\pm}4{\mu}m$. As a general three-layered table takes working range from several centimeters and a few tens of centimeters, it has disadvantages compared with precision positioning table, such as larger working range and rough accuracy. In this paper we design and implement a parallel $XY{\theta}$ table with three linear actuators, where one is on the horizontal direction and the others on the vertical direction on behalf of a degree of $XY{\theta}$ freedom. Finally, the experimental results of precision positioning is showed by using new image processing algorithms with two CCD cameras.

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Design Space Exploration of Many-Core Processor for High-Speed Cluster Estimation (고속의 클러스터 추정을 위한 매니코어 프로세서의 디자인 공간 탐색)

  • Seo, Jun-Sang;Kim, Cheol-Hong;Kim, Jong-Myon
    • Journal of the Korea Society of Computer and Information
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    • v.19 no.10
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    • pp.1-12
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    • 2014
  • This paper implements and improves the performance of high computational subtractive clustering algorithm using a single instruction, multiple data (SIMD) based many-core processor. In addition, this paper implements five different processing element (PE) architectures (PEs=16, 64, 256, 1,024, 4,096) to select an optimal PE architecture for the subtractive clustering algorithm by estimating execution time and energy efficiency. Experimental results using two different medical images and three different resolutions ($128{\times}128$, $256{\times}256$, $512{\times}512$) show that PEs=4,096 achieves the highest performance and energy efficiency for all the cases.

Acceleration of Feature-Based Image Morphing Using GPU (GPU를 이용한 특징 기반 영상모핑의 가속화)

  • Kim, Eun-Ji;Yoon, Seung-Hyun;Lee, Jieun
    • Journal of the Korea Computer Graphics Society
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    • v.20 no.2
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    • pp.13-24
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    • 2014
  • In this study, a graphics-processing-unit (GPU)-based acceleration technique is proposed for the feature-based image morphing. This technique uses the depth-buffer of the graphics hardware to calculate efficiently the shortest distance between a pixel and the control lines. The pairs of control lines between the source image and the destination image are determined by user's input, and the distance function of each control line is rendered using two rectangles and two cones. The distance between each pixel and its nearest control line is stored in the depth buffer through the graphics pipeline, and this is used to conduct the morphing operation efficiently. The pixel-unit morphing operation is parallelized using the compute unified device architecture (CUDA) to reduce the morphing time. We demonstrate the efficiency of the proposed technique using several experimental results.

Distributed In-Memory based Large Scale RDFS Reasoning and Query Processing Engine for the Population of Temporal/Spatial Information of Media Ontology (미디어 온톨로지의 시공간 정보 확장을 위한 분산 인메모리 기반의 대용량 RDFS 추론 및 질의 처리 엔진)

  • Lee, Wan-Gon;Lee, Nam-Gee;Jeon, MyungJoong;Park, Young-Tack
    • Journal of KIISE
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    • v.43 no.9
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    • pp.963-973
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    • 2016
  • Providing a semantic knowledge system using media ontologies requires not only conventional axiom reasoning but also knowledge extension based on various types of reasoning. In particular, spatio-temporal information can be used in a variety of artificial intelligence applications and the importance of spatio-temporal reasoning and expression is continuously increasing. In this paper, we append the LOD data related to the public address system to large-scale media ontologies in order to utilize spatial inference in reasoning. We propose an RDFS/Spatial inference system by utilizing distributed memory-based framework for reasoning about large-scale ontologies annotated with spatial information. In addition, we describe a distributed spatio-temporal SPARQL parallel query processing method designed for large scale ontology data annotated with spatio-temporal information. In order to evaluate the performance of our system, we conducted experiments using LUBM and BSBM data sets for ontology reasoning and query processing benchmark.

Research for Improving the Speed of Scrambler in the WAVE System (WAVE 시스템에서 스크램블러의 속도 향상을 위한 연구)

  • Lee, Dae-Sik;You, Young-Mo;Lee, Sang-Youn;Oh, Se-Kab
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37A no.9
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    • pp.799-808
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    • 2012
  • Bit operation of scrambler in the WAVE System become less efficient because parallel processing is impossible in terms of hardware and software. In this paper, we propose algorism to find the starting position of the matrix table. Also, when bit operation algorithm of scrambler and algorithms for matrix table, algorithm used to find starting position of the matrix table were compared with the performance as 8 bit, 16bit, 32 bit processing units. As a result, the number of processing times per second could be done 2917.8 times more in an 8-bit, 5432.1 times in a 16-bit, 10277.8 times in a 32 bit. Therefore, algorithm to find the starting position of the matrix table improves the speed of the scrambler in the WAVE and the receiving speed of a variety of information gathering and precision over the Vehicle to Infra or Vehicle to Vehicle in the Intelligent Transport Systems.

Efficient Cache Architecture for Transactional Memory (트랜잭셔널 메모리를 위한 효율적인 캐시 구조)

  • Choi, Dong-Min;Kim, Seung-Hun;Ro, Won-Woo
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.48 no.4
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    • pp.1-8
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    • 2011
  • Traditional transactional memory systems are no longer able to guarantee the performance of diverse applications with overflowed transactions since there is the drawback that tracking the data for logging is difficult. Especially, this mechanism has a disadvantage of increasing communication delay for sustaining the state which is required to detect the conflict on the overflowed transactions from the first level cache in the transactional memory systems. To address this point, we have focused on the cache architecture of the systems to reduce the overhead caused by overflows and cache misses. In this paper, we present Supportive Cache which reduces additional overhead during transactions. Supportive Cache performs a parallel look-up with L1 private cache and uses the same replacement policy as L1 private cache. We evaluate the performance of the proposed design by comparing LogTM-SE with and without Supportive Cache. The simulation results show that our system improves the performance by 37% on average, compared to the original LogTM-SE which uses the same hardware resource.

Establishing Model of Optimized Collaboration Procedure using PERT/CPM (PERT/CPM을 이용한 최적화된 협업 프로세스 수립 모형)

  • Lim, Yousup;Chang, Young-Hyeon;Kim, Seunghee
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.18 no.1
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    • pp.173-183
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    • 2018
  • It is a very difficult task to establish a collaborative procedure in a new business that requires multilateral collaboration or to revise the regulation by analyzing and proving objectively the problems in the collaborative process conducted already by multilateral collaboration. In this paper, we proposed an optimization model for collaborative process to establish the operation procedure between collaborative parties using PERT/CPM network diagram which allows us to calculate the processing time. In order to verify the effectiveness and usefulness of our model for the collaboration process optimization developed in this study, we applied the developed collaborative procedure to student selection of the work-and-study-in-parallel course associated with a degree executed by Ministry of Employment and Labor. This study can be useful not only for newly establishing or reconfiguring collaborative procedures but also for standardizing the business procedures for building information systems between collaborative organizations.

Parallel Spatial Join Method Using Efficient Spatial Relation Partition In Distributed Spatial Database Systems (분산 공간 DBMS에서의 효율적인 공간 릴레이션 분할 기법을 이용한 병렬 공간 죠인 기법)

  • Ko, Ju-Il;Lee, Hwan-Jae;Bae, Hae-Young
    • Journal of Korea Spatial Information System Society
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    • v.4 no.1 s.7
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    • pp.39-46
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    • 2002
  • In distributed spatial database systems, users nay issue a query that joins two relations stored at different sites. The sheer volume and complexity of spatial data bring out expensive CPU and I/O costs during the spatial join processing. This paper shows a new spatial join method which joins two spatial relation in a parallel way. Firstly, the initial join operation is divided into two distinct ones by partitioning one of two participating relations based on the region. This two join operations are assigned to each sites and executed simultaneously. Finally, each intermediate result sets from the two join operations are merged to an ultimate result set. This method reduces the number of spatial objects participating in the spatial operations. It also reduces the scope and the number of scanning spatial indices. And it does not materialize the temporary results by implementing the join algebra operators using the iterator. The performance test shows that this join method can lead to efficient use in terms of buffer and disk by narrowing down the joining region and decreasing the number of spatial objects.

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