• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• Journal of Korea Multimedia Society
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• v.21 no.2
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• pp.173-180
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• 2018

This paper proposes a method to improve the performance of face recognition via super-resolution method using sparse representation and deep learning from low-resolution facial images. Recently, there have been many researches on ultra-high-resolution images using deep learning techniques, but studies are still under way in real-time face recognition. In this paper, we combine the sparse representation and deep learning to generate super-resolution images to improve the performance of face recognition. We have also improved the processing speed by designing in parallel structure when applying sparse representation. Finally, experimental results show that the proposed method is superior to conventional methods on various images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.462-471
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• 1989

Two-dimensional median filters were affectively supprssing the noise in image processing with the adge smearing decreased. However, if the window were large as necessary in noise then the filter had tendency to cut off corners. An estimate of gradient was used to decide how the ouputs of the filters were calculated. For parallel to the gradient direction we used edge preserving median operation and orthogonal to that averaging subfilters over which medians were then chosen. Four different algorithms were introduced.

• Journal of the Korea Society for Simulation
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• v.5 no.2
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• pp.25-40
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• 1996

Modeling of systems for intensive knowledge-based processing requires a modeling methodology that makes efficient access to the information in huge data base models. The proposed level access mothodology is a modeling approach applicable to systems where data is stored in a hierarchical and modular modules of active memory cells(processor/memory pairs). It significantly reduces the effort required to create discrete event simulation models constructed in hierarchical, modular fashion for above application. Level access mothodology achieves parallel access to models within the modular, hierarchical modules(clusters) by broadcasting the desired operations(e.g. querying information, storing data and so on) to all the cells below a certain desired hierarchical level. Level access methodology exploits the capabilities of object-oriented programming to provide a flexible communication paradigm that combines port-to-port coupling with name-directed massaging. Several examples are given to illustrate the utility of the methodology.

• Journal of Information Display
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• v.1 no.1
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• pp.20-24
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• 2000

We propose on a novel vertical configuration (VC) for a helix-deformed ferroelectric liquid crystal (HDFLC) display that has fast response, high contrast, analog gray scale capability, and wide-viewing characteristics. In contrast to a conventional HDFLC in a planar geometry, smectic layers arrange themselves parallel to the substrates, and thus, extremely uniform alignment of molecules in large area is naturally achieved in our new configuration without additional processes such as the rubbing and/or electric field treatment. Moreover, with a proper design of electrode patterns on the same substrate, multidomain switching is easily realized without employing any complex process of alignment. Our new VC-HDFLC is expected to provide a viable technology to produce a next-generation large area LCD suitable for processing the dynamic image at a video-rate.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.91.5-91
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• 2001

This paper suggests that the immune algorithm can effectively be used in tuning of a PID controller. The artificial immune network always has a new parallel decentralized processing mechanism for various situations, since antibodies communicate to each other among different species of antibodies/B-cells through the stimulation and suppression chains among antibodies that form a large-scaled network. In addition to that, the structure of the network is not fixed, but varies continuously. That is, the artificial immune network flexibly self-organizes accord Eng to dynamic changes of external environment (meta-dynamics function). However, up to the present time, models based on the conventional crisp approach have been used to describe dynamic model relationship between antibody and antigen. Therefore, there are some problems ...

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.866-871
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• 1991

The multi-layer neural network possesses the desirable characteristics of parallel distributed processing and learning capacity, by which the uncertain variation of the parameters in the dynamically complex system can be handled adoptively. However the error back propagation algorithm that has been utilized popularly in the learning procedure of the mulfi-Jayer neural network has the significant limitations in the real application because of its slow convergence speed. In this paper, an approach to improve the convergence speed is proposed using the fuzzy logic that can effectively handle the uncertain and fuzzy informations by linguistic level. The effectiveness of the proposed algorithm is demonstrated by computer simulation of PUMA 560 robot manipulator.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.4
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• pp.26-36
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• 2000

This paper proposes a neural network algorithm for real-time multiprocessor scheduling problem. The proposed algorithm is developed base on Hopfield neural network for a benefit of parallel processing, in order to finish a requested task within a deadline time. To compare the performance of the proposed algorithm, we used EDA and LLA algorithm that has studied real-time multiprocessor scheduling before. The proposed algorithm is implemented hardware using VHDL.

• Korean Management Science Review
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• v.25 no.3
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• pp.45-57
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• 2008

This paper considers a genetic algorithm for sequencing activities and allocating resources to reduce the over all completion time of workflow in the presence resource constraints. The algorithm provides an integrated solution for two sub-problems. The first is to decide the priority for the activities which require the same resource. The other problem is to select one among available resources for each activity by considering the incurred setup time and the performance factor of each resource. We evaluate the algorithm performance for three different kinds of workflows including parallel structures. Computational results show that the proposed algorithm is more effective than a previous work.

• Journal of Korea Multimedia Society
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• v.20 no.2
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• pp.163-169
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• 2017

There are various algorithms evaluating a threshold for image segmentation. Among them, Otsu's algorithm sets a threshold based on the histogram. It finds the between-class variance for all over gray levels and then sets the largest one as Otsu's optimal threshold, so we can see that Otsu's algorithm requires a lot of the computation. In this paper, we improved the amount of computational needs by using estimated Otsu's threshold rather than computing for all the threshold candidates. The proposed algorithm is compared with the original one in computation amount and accuracy. we confirm that the proposed algorithm is about 29 times faster than conventional method on single processor and about 4 times faster than on parallel processing architecture machine.