• Journal of information and communication convergence engineering
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• v.22 no.2
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• pp.98-108
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• 2024

Scrypt is a password-based key derivation function proposed by Colin Percival in 2009 that has a memory-hard structure. Scrypt has been intentionally designed with a memory-intensive structure to make password cracking using ASICs, GPUs, and similar hardware more difficult. However, in this study, we thoroughly analyzed the operation of Scrypt and proposed strategies to maximize computational parallelism in GPU environments. Through these optimizations, we achieved an outstanding performance improvement of 8284.4% compared with traditional CPU-based Scrypt computations. Moreover, the GPU-optimized implementation presented in this paper outperforms the simple GPU-based Scrypt processing by a significant margin, providing a performance improvement of 204.84% in the RTX3090. These results demonstrate the effectiveness of our proposed approach in harnessing the computational power of GPUs and achieving remarkable performance gains in Scrypt calculations. Our proposed implementation is the first GPU implementation of Scrypt, demonstrating the ability to efficiently crack Scrypt.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• Transactions of Materials Processing
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• v.19 no.1
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• pp.38-43
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• 2010

Electromagnetic forming (EMF) method is one of high-velocity forming processes, which uses electromagnetic Lorentz force. Advantages of this forming technique are summarized as improvement of formability, reduction in wrinkling, non-contact forming and applications of various forming process. In this study, the EMF apparatus is developed. It is designed to be stored in 10 capacitors connected in parallel, each with a capacitance of $50{\mu}F$ and maximum working voltage of 5kV. The system has capacitance of $500{\mu}F$ and maximum stored energy of 6.25kJ. And EMF experiments are carried out to verify the feasibility of the EMF apparatus, which has enough forming force from the results of EMF experiment. In addition, peak current carrying a forming coil is predicted from theoretical background, and verified the predicted value compared with experimental value using the current measurement equipment. Consequently, EMF apparatus developed in this study can be applied to various EMF researches for commercialization.

• Journal of Korean Institute of Industrial Engineers
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• v.23 no.4
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• pp.769-778
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• 1997

Assembly/Disassembly Queueing Networks (ADQNs) with finite buffers have been used as a major tool for evaluating the performances of manufacturing and parallel processing systems. In this study, we present simple but effective methods which yield throughput upper and lower bounds for ADQNs with exponential service times and finite buffers. These methods are based on the monotonicity properties of throughputs with respect to service times and buffer capacities. The throughput-upper bounding method is elaborated on with general network configuration (specifically acyclic configuration). But our lower bounding method is restricted to the ADQNs with more specialized configuration. Computational experiments will be performed to confirm the effectiveness of our throughput-bounding methods.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09a
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• pp.388-391
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• 2003

We've been following research on the obstacle avoidance that is based on fuzzy control. We previously proposed a new method of automatically generating membership functions, which play an important role in improving accuracy of fuzzy control, by using genetic programming (GP). In this paper, we made two improvements to our proposed method, for the purpose of achieving better intelligence in fuzzy robots. First, the mutation rate is made to change dynamically, according to the coupled chaotic system. Secondly, the population partitioning using deme is introduced by parallel processing. The effectiveness of these improvements is demonstrated through several computer simulations.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.329-332
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• 1991

This paper presents an algorithm to reduce the time to solve Power Equations using a Neural Net. The Neural Net is trained with samples obtained through the conventional AC Load Flow. With these samples, the Neural Net is constructed and has the function of a linear interpolation network. Given arbitrary load level, this Neural Net generates voltage magnitudes and angles which are linear interpolation of real and reactive powers. Obtained voltage magnitudes and angles are substituted to Power Equations, Real and reactive powers are found. Thus, a new sample is generated. This new experience modifies weight matrix. Continuing to modify the weight matrix, the correct solution is achieved. comparing this method with AC Load flow, this method is faster. If we consider parallel processing, this method is far faster than conventional ones.

• Proceedings of the KOSOMBE Conference
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• v.1995 no.11
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• pp.278-281
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• 1995

In this paper, we have developed EEG (electroencephalography) analyzer for monitoring the condition of brain in neurological surgery. This system is composed of EEG amplifier. personal-computer and BSP (Digital Signal Processor). By parallel processing of DSP, this system can analysis the power spectral density change of EEG in real-time and display the CSA(Compressed Spectral Array) and CDSA(Color Density Spectral array) of EEG. This system was tested by real EEG and showed the change of EEG.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1028-1031
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• 1996

Dynamic scheduling is very important in constructing CIM and improving productivity of chemical processing systems. Computation at the scheduling level requires mostly a long time to generate an optimal schedule, so it is difficult to immediately respond to actual process events in real-time. To solve these problems, we developed dynamic scheduling algorithms such as DSMM(Dynamic Shift Modification Method), PUOM(Parallel Unit Operation Method) and UVVM(Unit Validity Verification Method). Their main functions are to minimize the effects of unexpected disturbances such as process time variations and unit failure, to predict a makespan of the updated dynamic schedule and to modify schedule desirably in real-time responding to process time variations. As a result, the algorithms generate a new pertinent schedule in real-time which is close to the original schedule but provides an efficient way of responding to the variation of process environment. Examples in a shampoo production batch process illustrate the efficiency of the algorithms.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.201-204
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• 2002

A large area inductively coupled plasma which is applicable to LCD processing is built with a modified single loop RF antenna. Combination of parallel and series paths of RF current through the antenna induces local enhancement of plasma density, which in turn provides uniform plasma density near the substrate. The plasma density distribution is measured and compared with that of the conventional single loop antenna. Aisotropic etching of photoresist is performed, and it is found that etch uniformity is improved by 3％ from 15% of the conventional etcher over 350$\times$300mm glass substrates. Photoresist etching rate and uniformity can be further improved by applying a periodic weak axial magnetic fieid.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.