• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.205-208
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• 2000

In this paper, a low voltage CMOS analog four-quadrant multiplier using two V-I converters is presented. The proposed V-I converter is composed of the series composite transistor and the low voltage composite transistor. The designed analog four-quadrant multiplier has simulated by HSPICE using 0.25$\mu\textrm{m}$ n-well CMOS process parameters with a 2V supply voltage. Simulation results show that the power dissipation is 1.55㎿, the cutoff frequency is 489MHz, and the THD can be 0.26％ at maximum differential input of 1V$\sub$p-p/.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.739-742
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• 2002

This article proposes a Four-Quadrant Analog Multiplier (4-QAM) applying switched-capacitor and pulse-width amplitude modulation (PWAM) principles. The features of the presented circuit are that it can function as analog multiplier with a wide dynamic range of input signal and no disturbing from deviation of carrier frequency of PWM signal. In addition, the circuit detail is simpler than that of the previously proposed circuits. It is then easy and applicable for employing it into Integrated Circuit (IC) realization to especially operate in low-frequency and low-power applications. The experimental results granted are in correspondence to the theoretical analysis.

• 한국전자통신학회논문지
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• 제15권3호
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• pp.479-486
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• 2020

이 논문에서는 아날로그 전류모드 인공지능 프로세서에서 핵심 디바이스 중에 하나인 아날로그 전류 모드 곱셈기 회로의 선형성과 동적범위 향상을 위한 설계 기법을 소개한다. 제안하는 회로는 4 quadrant Translinear loop를 NMOS 트랜지스터만으로 구성하여, 트랜지스터의 물리적 Mismatch를 최소화하는 설계로 0.35㎛ CMOS 공정에서 117㎛ × 109㎛로 구현가능하였으며, 최대 전고조파왜율 0.3% 의 선형성을 확보할 수 있었다. 제안한 아날로그 전류모드 곱셈기는 전류모드 인공지능 프로세서의 핵심 회로로 유용할 것으로 기대된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.658-661
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• 2002

An analog multiplier-divider circuit that realized through the use of OTAs, which does not require external passive circuit elements and temperature compensated, is proposed in this paper. Since the scheme is realized in such a way that employs only OTA as a standard cell, the circuit is simple and can be easily constructed from commercially available IC. The circuit bandwidth is wide and close to the transistor f$\sub$T/. Simulation results that demonstrate the performances of the multiplier-divider circuit are included.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.646-649
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• 2002

In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.

• 제어로봇시스템학회논문지
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• 제22권7호
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• 전자공학회논문지SC
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• 제37권2호
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• pp.43-49
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• 2000

본 논문에서는 저전압 저전력 시스템에 응용 가능한 CMOS 4상한 아날로그 멀티플라이어를 제안하였다. 제안된 멀티플라이어는 저전압에서 동작이 용이하며 아날로그 회로를 설계하는데 자주 이용되는 LV(Low-Voltage) 상보형 트랜지스터 방식의 특성을 이용하였다. LV 상보형 구조는 등가 문턱전압을 감소시킴으로서 회로의 동작전압을 감소시킬 수 있는 특징이 있다. 설계된 회로의 특성은 2V 공급전압하에서 0.6㎛ CMOS 공정파라미터를 갖는 HSPICE 시뮬레이션을 통하여 측정되었다. 이때 ±0.5V까지의 입력선형 범위내에서 선형성에 대한 오차는 1%미만이었다. 또한 -3㏈ 점에서의 대역폭은 290㎒, 그리고 전력소모는 373㎼값을 나타내었다.

• 대한전자공학회논문지
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• 제2권2호
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• pp.9-16
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• 1965

The characteristics of electronic multipliers and their accuracy are analyzed. From the analysis a low cost, four-quadrant timedivision electronic multiplier jis built. This multiplier produces an output voltage equal to 0.01 of the instantaneous product of two input voltage representing independent variables. Each input may either be constant or vary with time over a range of ${\pm}$100 volts. Drift and noise in this multiplier are kept at very low level and dynamic response is below 0.5 decibels up to 700 cycles per second. Methods of testing this multiplier and the results are also described. It is shown that the results agree with theoretical values satisfactorily.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
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• pp.121-124
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• 2004

In this paper, Simple and inexpensive analog maximum power point tracker (MPPT) algorithm for photovoltaic power system and low power system of doesn't use digital signal processor (DSP). The control circuit is composed such that the actual current and voltage are sensed directly from the PV array. These two signals are then multiplied by a single-chip multiplier. The multiplier output go through different time constants genesis pulse width modulated to switch. Finally those were verified through simulation.

• ETRI Journal
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• 제34권2호
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.