• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.183-195
• /
• 2012

We propose a variable-latency Decimal Floating Point(DFP) adder which adopts the dual data path scheme. It is to speed addition and subtraction of operand that has identical exponents. The proposed DFP adder makes use of L. K. Wang's operand alignment algorithm, but operates through high speed data-path in guaranteed accuracy range. Synthesis results show that the area of the proposed DFP adder is increased by 8.26% compared to the L. K. Wang's DFP adder, though critical path delay is reduced by 10.54%. It also operates at 13.65% reduced path than critical path in case of an operation which has two DFP operands with identical exponents. We prove that the proposed DFP adder shows higher efficiency than L. K. Wang's DFP adder when the ratio of identical exponents is larger than 2%.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.2
• /
• pp.53-64
• /
• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.3
• /
• pp.33-42
• /
• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.13 no.2
• /
• pp.180-187
• /
• 2010

In this paper, a global path generation method is suggested using multiple grid maps connected with the mission type of unmanned combat vehicle(UCV). In order to carry out a mission for UCV, it is essential to find a global path which is coincident with the characteristics of the mission. This can be done by considering various combat circumstances represented as grid maps such as velocity map, threat map and communication map. Cost functions of multiple grid maps are linearly combined and normalized to them simultaneously for the path generation. The proposed method is realized using $A^*$, a well known search algorithm, and cost functions are normalized in the ratio of the traverse time which is one of critical information should be provided with the operators using the velocity map. By the experiments, it is checked found global paths match with the mission type by reflecting input data of grid maps properly and the computation time is short enough to regenerate paths in real time as combat circumstances change.

• Structural Engineering and Mechanics
• /
• v.71 no.2
• /
• pp.139-151
• /
• 2019

In a project schedule, it is possible to reduce the time required to complete a project by allocating extra resources for critical activities. However, accelerating a project causes additional expense. This issue is addressed by finding optimal set of time-cost alternatives and is known as the time-cost trade-off problem in the literature. The aim of this study is to identify the optimal set of time-cost alternatives using a multiobjective teaching-learning-based optimization (TLBO) algorithm integrated with the non-dominated sorting concept and is applied to successfully optimize the projects ranging from a small to medium large projects. Numerical simulations indicate that the utilized model searches and identifies optimal / near optimal trade-offs between project time and cost in construction engineering and management. Therefore, it is concluded that the developed TLBO-based multiobjective approach offers satisfactorily solutions for time-cost trade-off optimization problems.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.21 no.1
• /
• pp.147-161
• /
• 1996

Generally the Multiprocessor Scheduling (MPS) problem is difficult to solve because of the precedence of the tasks, and it takes a lot of time to obtain its optimal solution. Though Genetic Algorithm (GA) does not guarantee the optimal solution, it is practical and effective to solve the MPS problem in a reasonable time. The algorithm developed in this research consists of a improved GA and GP/MISF (Critical Path/Most Immediate Successors First). An efficient genetic operator is derived to make GA more efficient. It runs parallel CP/MISF with GA to complement the faults of GA. The solution by the developed algorithm is compared with that of CP/MISF, and the better is taken as a final solution. As a result of comparative analysis by using numerical examples, although this algorithm does not guarantee the optimal solution, it can obtain an approximate solution that is much closer to the optimal solution than the existing GA's.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 1995.09a
• /
• pp.220-229
• /
• 1995

Generally the Multiprocessor Scheduling(MPS) problem is difficult to solve because of the precedence of the tasks, and it takes a lot of time to obtain its optimal solution. Though Genetic Algorithm(GA) does not guarantee the optimal solution, it is practical and effective to solve the MPS problem in a reasonable time. The algorithm developed in this research consists of a improved GA and CP/MISF(Critical Path/Most Immediate Successors First). A new genetic operator is derived to make GA more efficient. It runs parallel CP/MISF with Ga to complement the faults of GA. The solution by the developed algorithm is compared with that of CP/MISF, and the better is taken as a final solution. As a result of comparative analysis by using numerical examples, although this algorithm does not guarantee the optimal solution, it can obtain an approximate solution that is much closer to the optimal solution than the existing GA's.

• Korean Journal of Artificial Intelligence
• /
• v.12 no.2
• /
• pp.17-23
• /
• 2024

Various methods have been developed to predict the flight path of an air-launched weapon to intercept a fast-moving target in the air. However, it is also getting more challenging to predict the optimal firing zone and provide it to a pilot in real-time during engagements for advanced weapons having new complicated guidance and thrust control. In this study, a method is proposed to develop an optimized weapon engagement zone by the SCG (Scaled Conjugate Gradient) algorithm to achieve both accurate and fast estimates and provide an optimized launch display to a pilot during combat engagement. SCG algorithm is fully automated, includes no critical user-dependent parameters, and avoids an exhaustive search used repeatedly to determine the appropriate stage and size of machine learning. Compared with real data, this study showed that the development of a machine learning-based weapon aiming algorithm can provide proper output for optimum weapon launch zones that can be used for operational fighters. This study also established a process to develop one of the critical aircraft-weapon integration software, which can be commonly used for aircraft integration of air-launched weapons.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.9
• /
• pp.1892-1897
• /
• 2012

In this paper, efficient CNU(Check Node Update) algorithms are analyzed for high speed LDPC decoding in DVB-S2 standard. In aspect to CNU methods, there are some kinds of CNU methods. Among of them, MP (Min Product) method is quite often used in LDPC decoding. However MP needs LUT (Look Up Table) that is critical path in LDPC decoding speed. A new SC-NMS (Self-Corrected Normalized Min-Sum) method is proposed in the paper. NMS needs only normalized scaling factor instead of LUT and compensates the overestimation of MP approximation. In addition, SC method is proposed. It gives a faster convergence toward a decoded codeword. If a message change its sign between two iterations, it is not reliable and to avoid to propagate noisy information, its module is set to 0. The performance of SC-NMS has a little degrade compare to MP by 0.1 dB, however considering computational complexity and decoding speed, SC-NMS algorithm is optimal method for CNU algorithm.

• Convergence Security Journal
• /
• v.16 no.7
• /
• pp.113-120
• /
• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.