• Title/Summary/Keyword: algebraic soft-decision decoding

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A COMPLEXITY-REDUCED INTERPOLATION ALGORITHM FOR SOFT-DECISION DECODING OF REED-SOLOMON CODES

  • Lee, Kwankyu
    • Journal of applied mathematics & informatics
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    • v.31 no.5_6
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    • pp.785-794
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    • 2013
  • Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

Area-efficient Interpolation Architecture for Soft-Decision List Decoding of Reed-Solomon Codes (연판정 Reed-Solomon 리스트 디코딩을 위한 저복잡도 Interpolation 구조)

  • Lee, Sungman;Park, Taegeun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.3
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    • pp.59-67
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    • 2013
  • Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.