• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.120-123
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• 2000

Bridge Type Cell structure informed that the efficiency is increased by about 30% compared to the conventional type has been investigated during addressing period. As a result, the addressing time is decreased by about 20% compared to the conventional type. And wall charge distribution was analyzed Quantitatively in three electrodes during addressing period.

• Journal of Information Display
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• v.1 no.1
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• pp.42-47
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• 2000

The relationship between driving voltage and the amount of wall charge in the address period of surface discharge type AC Plasma Display Panel has been investigated. The amount of wall charge on each electrode is obtained simultaneously from the current profiles after applying only one addressing discharge pulse. The wall charge $Q_y$ on the scan electrode Y is almost the sum of $Q_x$ on the address electrode X and $Q_z$ on the sustain electrode Z. The $Q_y$ increased with the driving voltage regardless of the kind of electrode, whereas the addressing $T_d$ decreased. The $Q_x$ and $Q_y$ are increased considerably by blocking voltage $V_z$, whereas $Q_x$ is decreased. The $V_z$ dependence of $Q_x$ $Q_y$ and ${\varrho}_z$ in addressing discharge was $-13{\times}10^{-2}$ (pc/$V_z$), and $60{\times}10^{-2}$ ($pc/V_z$) and $70{\times}10^{-2}(pc/V_z)$, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.13-21
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• 2001

The discharge characteristics of 3 electrcdes AC surface discharge plasma display were analyzed. For an unstable state of the discharge which appeared at the maximum discharge voltage, it is found that a parbal erase of the wall charge by the second discharge is a cause. Based on the second discharge, new operation margin considering the interrelation between the address discharge and the display discharge was defined and the validity of it was verified by the experiments. It is necessary to decrease the acklress pulse width for high-speed addressing. However, the operation margin of the ackIress pulse decreases as the pulse width of it becomes narrower. If the address pulse width is wider than l[ps], the operation margin of the display discharge is not related to the address pulse width. From the experimental result, image or 8bit 253 gray level was displayed on PDP with the cell structure of the HDTV class by using the high-speed address ADS drive methcd with pulse width of $1[{\mu}s]$ and the brightness of $560[cd/m^2]$ was obtained. ained.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.267-273
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• 2003

The plasma display panel with the electrode structure of new discharge AND gate and its driving scheme were proposed and the driving system for experiment was developed. And operation of these discharge AND gate was verified by the experiment of PDP addressing with floating electrode. This discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 100V. The address operation margin of 10V also obtained. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because proposed method uses the DC discharge the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of discharge gate are separate, the display discharge can be prevented from passing discharge gates. Therefore, it is possible to apply to the large screen plasma display panel. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.7
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• pp.13-19
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• 2007

This study relates to a new high-speed drive method for the full-HD PDP with 1080 horizontal scanning lines. The characteristics of the new drive method is evaluated considering the characteristics of the display discharge by the high-speed addressing. In this drive method, if the width of the address pulse narrows, the relati0[V]e discharge strength and the discharge time lag of the first display discharge are received the influence of it. Though the change in the applied position of the address pulse is unrelated to the discharge strength, it influences at the discharge time lag. However, the stable display discharges can be induced regardless of the address pulse position and width if the address pulse position is within [$6{\mu}s$] and the width is up to [$0.7{\mu}s$]. From the experiments, it has been understood that the high-speed drive technique with the address pulse of narrow width is sensitively influenced by the space charge because of the insufficiency of wall charge.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.103-107
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• 2000

The relationships between driving voltage and the wall charge distribution in the address period of surface discharge type AC Plasma Display Panel have been investigated. The quantity of wall charge on each electrode are detected simultaneously from the electrode current after applying only one addressing discharge pulse. The wall charge Qy on the scan electrode Y is nearly the sum of Qx on the address electrode X and Qz on the sustain electrode Z. The Qy increased with the driving voltage regardless of the kind of electrode, whereas the address time Td decreased, Qz and Qy are increased considerably with the blocking voltage Vz, whereas Qx is decreased. The increase rate of Qx, Qy and Qz for increase in Vz was $-13{\times}10^{-2}$ (pc/Vz), and $60{\times}10^{-2}$ (pc/Vz) and $70{\times}10^{-2}$(pc/Vz), respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.726-729
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• 2003

A new driving method is proposed to reduce the address period. The scan time of new driving method overlaps with the next scan time during the discharge lag time. Thus, without reducing the address pulse width and the scan pulse width, the new addressing method can reduce the address period. The results show that the scan time of about 100ns ${\sim}$ 300ns can be overlapped without the misfiring,.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.706-709
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• 2003

We made an optimization effort on driving waveforms for the Quantized Memory Addressing (QMA) in selective write mode of operation. It was necessary to add long ramp type erase pulses after the total write pulse and the sustain period to obtain stable intermediate luminance discharges. Furthermore, fast rising ramp type total write as well as two step addressing scheme were adopted for better discharge stability.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.11-14
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• 2006

A new reset waveform with negative ramp pulse is proposed. Conventional reset waveform applied to the commercial PDP uses a positive ramp pulse. The reset waveforms, especially focused on ramp area, were examined with 2 dimensional fluid code. The proposed negative reset waveform showed much lower ignition voltage ($\sim$70V) as compared with the conventional reset waveform. When the negative ramp pulse was applied, all of the positive-charged ions are collected on the scan electrode. It is found that the ignition voltage of reset discharge due to the negative ramp pulse became lower than that of positive ramp discharge.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1587-1591
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• 2015

For a higher definition discharge cell, the method of high speed addressing is necessary. In order to modify the surface charges, the liquefied $TiO_2$ or MgO powder is added on MgO layer in front glass and on the phosphor in rear glass in micro barrier discharge. Both the electro-optical properties and the discharge time lag characteristics are measured from 4 inch. test panel, such as the discharge voltage, current, luminance, luminous efficacy and discharge time lag. As the results, the statistic time lag is improved by about 40 %.