• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1286-1294
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• 2015

Capacitor current feedback active damping is extensively used in grid-connected converters with an LCL filter. However, systems tends to become unstable when the digital control delay is taken into account, especially in low switching frequencies. This paper discusses this issue by deriving a discrete model with a digital control delay and by presenting the stable region of an active damping loop from high to low switching frequencies. In order to overcome the disadvantage of capacitor current feedback active damping, this paper proposes a modified approach using grid current and converter current for feedback. This can expand the stable region and provide sufficient active damping whether in high or low switching frequencies. By applying the modified approach, the active damping loop can be simplified from fourth-order into second-order, and the design of the grid current loop can be simplified. The modified approach can work well when the grid impedance varies. Both the active damping performance and the dynamic performance of the current loop are verified by simulations and experimental results.

• Journal of Power Electronics
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• v.9 no.3
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• pp.365-376
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• 2009

In this paper, the implementation of a three-phase shunt active power filter is presented. The filter is essentially three independent single-phase current-controlled voltage source inverters (CC-VSI) with a common DC bus. The CC- VSI is operated to directly control the AC grid current to be sinusoidal and in phase with the grid voltage without detecting the load currents. The APF consists of a current control loop, which shapes the grid currents to be sinusoidal and a voltage control loop, which regulates the active power balance of the system. The experimental results indicate that the active filter is able to handle predominantly the harmonics, as well as the unbalance and reactive power, so that the grid currents are sinusoidal, in phase with the grid voltages and symmetrical.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1165-1177
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• 2018

This paper investigates the active damping of grid-connected LCL filter resonance using high-pass filter (HPF) of the grid current. An expression for such HPF is derived in terms of the filter components. This expression facilitates a general study of the actively damped filter behavior in the discrete time domain. Limits for the HPF parameters are derived to avoid the excitation of unstable open loop poles since such excitation can reduce both the damping performance and the system robustness. Based on this study, straightforward co-design steps for the active damping loop along with the fundamental current regulator are proposed. A numerical example along with simulation and experimental results are presented to verify the theoretical analyses.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.6
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• pp.546-554
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• 2012

This paper suggests a design method of an improved phase control loop for tracking resonant frequency of solid type precision resonant gyroscope. In general, a low cost MEMS gyroscope adapts the automatic gain control loops by taking a velocity feedback configuration. This control technique for controlling the resonance amplitude shows a stable performance. But in terms of resonant frequency tracking, this technique shows an unreliable performance due to phase errors because the AGC method cannot provide an active phase control capability. For the resonance control loop design of a solid type precision resonant gyroscope, this paper presents a phase domain control loop based on linear PLL (Phase Locked Loop). In particular, phase control loop is exploited using a higher order PLL loop filter by extending the first order active PI (Proportion-Integral) filter. For the verification of the proposed loop design, a hemispherical resonant gyroscope is considered. Numerical simulation result demonstrates that the control loop shows a robust performance against initial resonant frequency gap between resonator and voltage control oscillator. Also it is verified that the designed loop achieves a stable oscillation even under the initial frequency gap condition of about 25 Hz, which amounts to about 1% of the natural frequency of a conventional resonant gyroscope.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.233-236
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• 2005

Phase noise in a phase-locked-loop (PLL) is unwanted and unavoidable. It is a main concern in oscillation system especially PLL. The phase noise is derived in term of power spectrum density by using a reliable phase noise model. There are four noise sources being considered in this paper, which are generated by reference oscillator, voltage controlled oscillator, filter, and main divider. The major concern for this paper is the noise from the filter. Two types of second order low pass filter are used in the PLL system. Applying the mathematical phase noise model, the output noises are compared. The total noise from the passive filter is lower than the active filter at the offset frequency range between 1 Hz to 33 kHz.

• Journal of Power Electronics
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• v.12 no.5
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• pp.800-812
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• 2012

This paper analyses the mathematical model and control strategies of a Hybrid Active Power Filter with Injection Circuit (IHAPF). The control strategy based on the load harmonic current detection is selected. A novel control method for a IHAPF, which is based on the analyzed control mathematical model, is proposed. It consists of two closed-control loops. The upper closed-control loop consists of a single fuzzy logic controller and the IHAPF model, while the lower closed-control loop is composed of an Adaptive Network based Fuzzy Inference System (ANFIS) controller, a Neural Generalized Predictive (NGP) regulator and the IHAPF model. The purpose of the lower closed-control loop is to improve the performance of the upper closed-control loop. When compared to other control methods, the simulation and experimental results show that the proposed control method has the advantages of a shorter response time, good online control and very effective harmonics reduction.

• Transactions of the Korean Society of Automotive Engineers
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• v.11 no.6
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• pp.222-228
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• 2003

Lane departure avoidance system is one of the key technologies for the future active-safety passenger cars. The lane departure avoidance system is composed of two subsystems; lane sensing algorithm and active-steering controller. In this paper, the road image is obtained by vision sensor and the lane parameters are estimated using image processing and Kalman Filter technique. The active-steering controller is designed to prevent the lane departure. The developed active-steering controller can be realized by steer-by-wire actuator. The lane-sensing algorithm and active-steering controller are implemented into the steering HILS(Hardware-In-the-Loop Simulation) and their performance is evaluated with a human driver in the loop.

• ETRI Journal
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• v.38 no.2
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• pp.217-226
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• 2016

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of $0.098mm^2$ and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.520-523
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• 2004

A phase-locked loop control system designed by using the linear quadratic regulator approach is presented in this paper. The system thus designed is optimal system when system is in locked state and the parameter value of loop filter which is an active PI filter can be obtained easily. By considering the structure of loop filter of phase-locked loop is included in the process to be controlled, a type 1 servo system can be constructed when voltage control oscillator is considered as an integrator. The integral gain of the proposed system obtained by linear quadratic regulator approach can be used as an optimal value to design the parameter of loop filter. The implemented result in controlling the second-order lag pressure process by using the proposed scheme show that the system response is fast with no overshoot and no steady-state error. Furthermore, the experimental results are also shown in term of output disturbance effect rejection, tracking and process parameter changed.