• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.44-48
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• 2008

Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.713-719
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• 2000

In order to Prepare the$Ge_xSi_{1-x}/Si$(111) heterosructure by solid phase epitaxy (SPE), about 1000A of Au and about 1000A Ge were sequentially deposited on the Si(111) substrate. The resulting Ge/Au/Si(111) samples were isochronically annealed in the high vacuum condition. The behaviors of Au and Ge during thermal annealing and the structural Properties of $Ge_xSi_{1-x}$ films were characterized by Auger electron spectroscopy (AES), X-ray diffraction (XRD) and high resolution transmission electron microscopy (TEM). The a-Ge/Au/Si(111) structure was converted to the Au/GeSi/Si(111) structure. Defects such as stacking faults, point defects and dislocations were found at the GeXSil-X(111) interface, but the film was grown epitaxially with the matching face relationship of $Ge_xSi_{1-x}/$(111)/Si(111). Twin crystals were also found in the $Ge_xSi_{1-x}/$(111) matrix.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of the Korean Ceramic Society
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• v.37 no.5
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• pp.432-437
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• 2000

Thermoelectric properties of p-type SiGe alloys prepared by a RF inductive furnace were investigated. Non-doped Si80Ge20 alloys were fabricated by control of the quantity of volatile Ge. The carrier of p-type SiGe alloy was controlled by B-doping. B doped p-type SiGe alloys were synthesized by melting the mixture of Ge and Si containing B. The effects of sintering/annealing conditions and compaction pressure on thermoelectric properties (electrical conductivity and Seebeck coefficient) were investigated. For nondoped SiGe alloys, electrical conductivity increased with increasing temperatures and Seebeck coefficient was measured negative showing a typical n-type semiconductivity. On the other hand, B-doped SiGe alloys exhibited positive Seebeck coefficient and their electrical conductivity decreased with increasing temperatures. Thermoelectric properties were more sensitive to compaction pressure than annealing time. The highest power factor obtained in this work was 8.89${\times}$10-6J/cm$.$K2$.$s for 1 at% B-doped SiGe alloy.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.83.1-83.1
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• 2010

Hydrogenated a-SiGe middle cell for triple junction solar cell was investigated with various process parameters. a-SiGe I-layer was deposited at substrate temperature $245^{\circ}C$ and hydrogen content(R) was up to 26.7. Low optical bandgap(1.45eV) of a-SiGe cell was applied for middle cell although a-SiGe single cell efficiency with low Ge content was higher. And this cell was applied to the middle cell of a glass superstrate type a-Si/a-SiGe/uc-Si triple junction solar cell. The triple junction solar cell was resulted in the initial efficiency of about 9%, area $0.25cm^2$, under global AM 1.5 illumination.

• Journal of the Korean Vacuum Society
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• v.20 no.2
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• pp.77-85
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• 2011

The silicon-germanium (SiGe) alloy, which is compatible with silicon semiconductor technology and has a smaller band gap and a lower thermal conductivity than silicon, has been used to fabricate electronic devices such as transistors, photodetectors, solar cells, and thermoelectric devices. This paper reviews the application of SiGe alloys to electronic devices and related technical issues. Since the SiGe alloy comprises germanium whose band gap is smaller than silicon, its band gap is also smaller than that of silicon irrespective of the ratio of silicon to germanium. This narrow band gap of SiGe enables the base thickness of bipolar transistors to decrease without a loss in current gain so that it is possible to improve the speed of bipolar transistors by adopting the SiGe-base. In addition, the conversion efficiency of solar cells is enhanced by the absorption of long-wavelength light in the SiGe absorption layer. Phonon scattering caused by the irregular distribution of alloying elements induces the lower thermal conductivity of SiGe than those of pure silicon and germanium. Because a thin film layer with a low thermal conductivity suppresses thermal conduction through a thermal sink, the SiGe alloy is considered to be a promising material for silicon-based thermoelectric systems.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.86-92
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• 1999

A SiGe p-channel MESFET using $\delta$-doped layers is designed and the considerabel enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta$-doped layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes in the spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of 0~300$\AA$ and the Ge composition of 0~30% are investigated, and saturation current is observed to be increased by 45% compared with a double $\delta$-doped Si p-channel MESFET.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.541-544
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• 1998

A SiGe p-channel MESFET using $\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of $0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double $\delta-doped$ Si p-channel MESFET.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.