• Korean Journal of Materials Research
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• v.23 no.1
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

• Journal of the Korean Ceramic Society
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• v.27 no.3
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• pp.412-422
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• 1990

Porous SiC ceramics were proposed to be promising materials for high-temperature thermoelectric energy conversion. Throughthe thermoelectric property measurements and microstructure observations on the porous alpha SiC and the mixture of $\alpha$-and $\beta$-SiC, it was experimentally clarified that elimination of stacking faults and twin boundaries by grain growth is effective to increase the seebeck coefficient and increasing content of $\alpha$-SiC gives rise to lower electrical conductivity. Furthermore, the effects of additives on the thermoelectric properties of 6H-SiC ceramics were also studied. The electrical conductivity and the seebeck coefficient were measured at 35$0^{\circ}C$ to 105$0^{\circ}C$ in argon atmospehre. The thermoelectric conversion efficiency of $\alpha$-SiC ceramics was lower than that of $\beta$-SiC ceramics. The phase homogeneity would be needed to improve the seebeck coefficient and electrical conductivity decreased with increasing the content of $\alpha$-phase. In the case of B addition, XRD analysis showed that the phase transformation did not occur during sintering. On the other hand, AlN addiiton enhanced the reverse phase transformation from 6H-SiC to 4H-SiC, and this phenomenon had a great effect upon the electrical conductivity.

• 한국신재생에너지학회:학술대회논문집
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• 2005.11a
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• pp.191-202
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• 2005

비정질 실리콘 태양전지 대신에 열화가 더 적은 프로터결정 실리콘(pc-Si:H)을 상층전지 흡수층으로 사용한 고효율 실리콘계 적층형(pc-Si:H/$\mu$c-Si:H) 박막 태양전지를 개발하였다. 우선, 높은 전도도와 넓은 에너지 밴드갭 특성을 갖는 p-a-SiC:H 박막을 개발하였고, p/i 계면의 특성 향상을 위해 p-nc-SiC:H 완충층을 개발하였다. 프로터결정 실리콘 다층막을 제작하고 FTIR, 평면 TEM, 단면 TEM 측정을 통해 프로터결정 실리콘 다층막의 우수한 열화 특성의 원인을 규명하였다. 적층형 태양전지의 성능향상을 위해 n-p-p 구조의 터널접합을 제안, 제작하고 특성을 분석하였으며, pc-Si:H/a-Si:H 적층형 태양전지에 적용하여 성능향상을 이루었다. 양질의 하층전지용 마이크로결정 실리콘 박막을 증착하기 위하여 광CVD법과 플라즈마CVD법을 결합한 2단계 마이크로결정 실리콘 증착법을 개발하였다.

• 한국신재생에너지학회:학술대회논문집
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• 2009.06a
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• pp.28-30
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• 2009

이종접합태양전지에서 p a-Si:H/c-Si의 p a-Si:H의 증착 조건인 $H_2/SiH_4$ 비율, $B_2H_6$의 농도를 변화 시키며 실험하여 이 따라 계면 특성 변화를 연구하였다. pa-Si:H의 $H_2/SiH_4$ 비율이 상승할수록 carrier lifetime이 증가하다 다시 감소하는 경향을 나타내었다. 이는 $H_2/SiH_4$의 비율 중 효과적으로 웨이퍼표면을 효과적으로 passivation하는 지점이 있는 것으로 보인다. $B_2H_6$의 농도는 상승할수록 carrier lifetime이 줄어드는 경향을 보였다. $B_2H_6$에서 농도가 올라감에 웨이퍼 표면의 defect로 작용했을 것으로 생각된다. 이에서 몇몇의 조건으로 태양전지를 제작한 결과 $H_2/SiH_4$ 비율에 따라서는 carrier lifetime은 효율에 그 영향이 미미한 것으로 조사되었고, $B_2H_6$의 농도가 낮을수록 개방전압은 상승하는 결과를 얻어 도핑 농도가 효율에 직접적인 형향을 주는 것으로 나타났다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.3
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• pp.303-308
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• 1999

As a semiconductor material for electronic devices operated under extreme environmental conditions, silicon carbides(SiCs) have been intensively studied because of their excellent electrical, thermal and other physical properties. The growth characteristics of single-crystalline 4H-SiC homoepitaxial layers grown by a thermal chemical vapor deposition (CVD) were investigated. Especially, the successful growth condition of 4H-SiC homoepitaxial layers using a SiC-uncoated atmospheric pressure chamber and carried out using off-oriented substrates prepared by a modified Lely method. In order to investigate the crystallinity of grown epilayers, Nomarski optical microscopy, Raman spectroscopy, photoluninescence(PL), scanning electron microscopy(SEM) and other techniques were utilized. The best quality of 4H-SiC homoepitaxial layers was observed in conditions of growth temperature $1500^{\circ}C$ and C/Si flow ratio 2.0 of $C_{3}H_{8}\;0.2\;sccm\;&\;SiH_{4}\;0.3\;sccm$. The growth rate of epilayers was about $1.0\mu\textrm{m}/h$ in the above growth condition.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• Journal of the Korean Ceramic Society
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• v.48 no.6
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• pp.621-624
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• 2011

In order to deposit a homogeneous and uniform ${\beta}$-SiC films by chemical vapor deposition, we constructed the phase-diagram of ${\beta}$-SiC over graphite and silicon via computational thermodynamic calculation considering pressure(P), temperature(T) and gas composition(C) as variables in $C_3H_8-SiCl_4-H_2$ system. During the calculation, the ratio of Cl/Si and C/Si is maintained to be 4 and 1, respectively, and H/Si ratio is varied from 2.67 to 15,000. The P-T-C diagram showed very steep phase boundary between SiC+C and SiC region perpendicular to H/Si axis and also showed SiC+Si region with very large H/Si value of ~6700. The diagram can be applied not only to the prediction of the deposited phase composition but to compositional variation due to the temperature distribution in the reactor. The P-T-C diagram could provide the better understanding of chemical vapor deposition of silicon carbide.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.2
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• pp.101-109
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• 2002

A complex chemical equilibrium analysis was performed to study the hot-wall CVD process of the SiC/C functionally gradient materials (FGM). Thermochemical calculations of the Si-C-H-Cl system were carried out, and the effects of process variables(deposition temperature, reactor pressure, C/[Si+C] and H/[Si+C] ratios in the source gas) on the composition of deposited layers and the deposition yield were investigated. The CVD phase diagrams of the SiC/C FGM deposition were obtained, and the optimum process windows were estimated from the results.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.129.1-129.1
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• 2011

a-Si:H/c-Si 구조의 이종접합 태양전지 전면 투명전도막으로 Indium tin oxide(ITO) 박막의 조건에 따라 태양전지 특성을 연구하였다. ITO 박막은 파우더 타겟으로 마그네트론 스퍼터링 방식으로 성막하였고, 증착 온도(Ts)에 따라 전기적, 광학적 특성을 비교, 분석하였다. 기판 증착 온도가 증가할수록 박막의 저항이 낮아지는 것으로 나타났으며 $350^{\circ}C$ 조건에서 가장 낮은 저항($34.2{\Omega}$/sq)을 보였다. 투과도 또한 기판 증착 온도가 올라갈수록 전반적인 향상을 나타냈다. a-Si:H/c-Si 기판의 MCLT(minority carrier lifetime)는 $350^{\circ}C$에서 최적($359{\mu}s$)의 결과를 나타냈다. 그 이상의 기판 온도에서는 오히려 감소하였는데, 이는 높은 온도에서의 a-Si:H/c-Si 계면의 열손상으로 판단된다.

• Journal of IKEEE
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• v.18 no.4
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• pp.447-455
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• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.