• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.352-354
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• 2008

A 15.4" WXGA TFT-LCD, featuring integrated a-Si:H gate driver circuits and reduced data driver ICs, has been developed. To reduce number of data lines into 1/2 of conventional structure, the pixel array has been re-mapped with re-organized data signal. Unintended artificial effects such as flicker were removed by adopting the novel pixel array having a 'zigzag' map. To minimize the power consumption, a column inversion method was incorporated in the zigzag pixel array (Fig.1) without modifying the polarity map of conventional dot inversion method.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.517-520
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• 2008

A voltage-programming pixel circuit, which compensates the threshold voltage shift of TFTs and the degradation of OLED, is proposed for large sized a-Si:H active matrix organic light emitting diode (AMOLED) applications. Considering threshold voltage variation (or shift), OLED degradation and reverse bias annealing, HSPICE simulation results indicate that luminance error of every gray level is less than 0.4 LSB under the condition of +1V threshold voltage shift and from -0.2 LSB to 2.6 LSB within 30% degradation of OLED in the case of 40-inch full HDTV condition.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.348-351
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• 2007

A pure polyimide substrate and polyimide substrate with nano-silica additive have been formed on glass by coating. The a-Si:H TFT arrays have been formed on such polyimide substrate for driving TNLCD.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.749-752
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• 2004

Unlike OLEDs, there is no lifetime testing procedure for TFTs. In this work, we have defined such a procedure and developed a method for the accelerated stress testing of TFT pixel circuits in a-Si AMOLED displays. The acceleration factors derived are based on high current and temperature stress, and can be used to significantly reduce the testing time required to guarantee a 20000-hour display backplane lifespan.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.258-258
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• 2011

최근 유연 기판을 이용한 태양전지 및 TFT 등 전자소자 개발에 관한 연구가 주목받고 있다. 본 연구에서는 공정 시 유리한 유리기판상 전자소자 제작 후 폴리이미드막 박리를 통한 유연전자 소자 구현을 목적으로 한다. 폴리이미드막 박리를 목적으로 희생층으로서 a-Si:H을 사용하였다. 유리기판상에 60 nm 두께의 a-Si : H을 ICP (Induced coupled plasma) 공정으로 증착한 후 a-Si : H층 상부에 30 ${\mu}m$ 두께로 폴리이미드를 코팅하여 Hot plate와 furnace에서 열처리를 거쳤다. 이후 각기 다른 파장을 갖는 레이저의 파워를 가변하며 유리 기판 후면에 조사하였다. 실험 결과 355 nm UV 레이저로 가공한 경우 희생층으로 사용 된 a-Si : H층 내에 존재하는 수소가 레이저 빛 에너지에 의해 결합이 끊어지면서 유리기판과 폴리이미드막이 분리됨을 확인하였다.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1008-1012
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• 1996

I-V, C-V characteristics of inverted staggered type hydrogenerated amorphous silicon thin film transistor(a-Si:H TFT) was studied and experimentally verified. The results show that the log-log plot of drain current increased by voltage increase. The saturated drain current of DC output characteristics increased at a fixed gate voltage. According to the increase of gate voltage, activation energy of electron and the increasing width of Id at high voltage were decreased. Id saturation current saturated at high Vd over 4.5V, Vg-ld hysteresis characteristic curves occurred between -15V and 15V of Vg. Hysteresis current decreased at low voltage of -15V and increased at high voltage of 15V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.627-629
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• 2004

본 연구는 자기정렬 방법을 기존의 방식과 다르게 적용하여 수소화 된 비정질 실리콘 박막 트랜지스터의 제조공정을 단순화하고, 박막 트랜지스터의 게이트와 소오스-드레인간의 기생용량을 줄인다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H 층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거한다. 그 위에 Cr층을 증착한 후 패터닝 하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 이렇게 제조하면 기존의 박막 트랜지스터에 비하여 특성은 같고, 제조공정은 줄어들며, 또한 게이트와 소오스-드레인간의 기생용량이 줄어들어 동작속도를 개선시킬 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.239-242
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• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.793-796
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• 2005

A structure and a design of device were developed to fabricate large-scale active matrix organic light-emitting diode (AMOLED) display with good color purity and high aperture ratio. With these technologies, we developed a full color 14.1 inch WXGA AMOLED display. For the integration of OLED on an active matrix a-Si TFT backplane, an efficient top emission OLED is essential since the TFT circuitry covers a large position of the pixel aperture. These technologies will enable up the OLED applications to larger size displays such as desktop monitors and TVs.