• Journal of Institute of Control, Robotics and Systems
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• v.6 no.5
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• pp.396-403
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• 2000

A thermal imaging system is implemented for the measurement and the analysis of the thermal distribution of the target objects. The main part of the system is a thermal camera in which a focal plane array typed sensor is introduced. The sensor detects the mid-range infrared spectrum of target objects and then it outputs a generic video signal which should be processed to form a frame thermal image. Here, a digital signal processor(DSP) is applied for the high speed processing of the sensor signals. The DSP controls analog-to-digital converter, performs correction algorithms and outputs the frame thermal data to frame buffers. With the frame buffers can be generated a NTSC signal and transferred the frame data to personal computer(PC) for the analysis and a monitoring of the thermal scenes. By performing the signal processing functions in the DSP the overall system achieves a simple configuration. Several experimental results indicate the performance of the overall system.

• Proceedings of the Acoustical Society of Korea Conference
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• 1984.12a
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• pp.63-65
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• 1984

In this paper, the implementation of the real time LPC synthesizer using NEC 77p20, the DSP (Digital Signal Processor) chip which facilitates and simplifies the digital hardware, is considered. This method shows the good quality with the low bit rate below 9.6kbps and has the advantage of the flexibility and the simplicity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.890-893
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• 2014

In this paper, we present a signal processing algorithm for a marine radar system, in which the evaluation of probability of collision as well as target detection and tracking are performed. Moreover, the digital signal processor that implements the algorithm is proposed. As simulation environment, a mechanically scanning antenna utilizing FMCW signal is used, conducting the beamforming operation with 1 degrees intervals. Test board consists of DSP chips and FPGA, which enable the implemented system to operate in real-time.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1178-1183
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• 1990

A digital signal processor(DSP) is applied to realizing a compensator of control system of active magnetic bearings, to restrict a resonance caused by the first-order bending vibration of a flexible rotor, and to run the rotor beyond the critical speed. A full-order observer is applied to the translatory rotor-motion with the first-order vibration mode. A PID control is used for the conical motion. The rotor used in the experiments is symmetric, and an electromagnet and a displacement sensor are set in collocation.

• Korean Journal of Optics and Photonics
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• v.14 no.6
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• pp.588-593
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• 2003

A signal processor for interferometeric fiber optic sensors, which measure dynamic quantities of frequency up to 1 KHz with high sensitivity, is developed. It is a high-speed version of the all-digital phase tracking (ADPT) processor that was used to measure static or slowly-varying quantities. The processor was applied to a fiber optic Mach-Zehnder interferometer to evaluate the performance. The measured total harmonic distortion was near to -50 ㏈, which is the theoretical limit or the ADPT signal processing.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1995.06a
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• pp.165-170
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• 1995

In this paper, it is attempted to apply the adaptive digital signal processing to compensate for a linear distortion of a loudspeaker and implement a real time hardware for that purpose. The real time system is implemented by using the DSP56001, a general purpose signal processor, as a host processor and the DSP56200, a cascadable adaptive FIR filter peripheral chip, as an adaptive digital filter. The system has 1000 taps at a 44.1kHz. After inverse modeling of under_compensation_speaker, the system reduces loudspeaker's linear distortions by pre-processing an input audio signal to loudspeaker. The experiment shows satisfactory results; after adaption with white noise as input signal for 60sec, the flat amplitude and linear phase frequency characteristics is found to lie over a wide frequency range of 100Hz to 20kHz.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.77-81
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• 2021

In this paper, a low-csst ECG system using a digital filter was implemented. After amplifying the analog ECG signal, it is converted into a digital signal and filtered. The developed ECG module is miniaturized by removing the analog filter element that occupies the existing volume and replacing it with a digital filter using a 3-stage Butterworth filter which is one of IIR filters. It uses a serial monitoring program with C# to check and save the ECG waveform measured on a computer screen. The ECG system using a developed digital filter in this paper uses a low-cost processor instead of an expensive, high-end processor, and its size and price are reduced by converting the analog filter to a digital filter. In addition, since the waveform of the developed ECG system is similar to the actual ECG waveform of MIT-BIU, it is considered that the existing analog filter can be replaced with the developed digital filter.

• Journal of Power Electronics
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• v.9 no.3
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• pp.410-417
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• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1217-1220
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• 2005

In this paper, statistical simulation is applied to a superscalar digital signal processor architecture using DSP kernel and DSP application benchmarks. As a result, the performance of a digital signal processor with several microarchitecture configurations can be estimated with the relative error of 3.7 ${\backslash}%$ on the average.