• Title/Summary/Keyword: Xc

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A Design and Development of DICOM Camera System (DICOM 카메라 시스템 설계 및 구현)

  • Jang, Dae-Jin
    • Proceedings of the Korea Information Processing Society Conference
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    • 2014.11a
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    • pp.349-351
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    • 2014
  • 최근 정부 및 의료산업계에서 원격진료에 대한 관심이 매우 대두되고 있다. 본 연구에서는 모바일 PACS 시스템을 개선한 XC(External Photography Camera) 유형의 DICOM 영상획득 장치 설계 및 개발 결과를 제시하며, 또한 고용량의 DICOM 이미지를 스마트기기에 효율적인 전송하기 위한 모바일 게이트웨이 설계 결과를 제시한다.

Decoding Algorithm of (128,124) RS Code for AAL-1 and Its FPGA Implementation (AAL-1 에 적용가능한 (128, 124) RS 부호의 복호 알고리즘과 FPGA 실현)

  • 염흥열
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.7 no.1
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    • pp.33-44
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    • 1997
  • BISDN(Broadband Integrated Service Digital Network)의 AAL-1(ATM Adaptation Layer-1)에서는 오류정정능력이 2인 (128,124) RS(Reed Slomon) 부호를 이용하여 ATM 셀에서 발생하는 오류를 정정하고 있다. 본 논문에서는 기존의 RS 복호 알고리즘을 분석한 후, 이를 바탕으로 AAL-1 기본오류정정 모드에 적용 가능한 복잡도가 낮고 고속 동작이 가능한 복호 알고리즘을 제시하고, 부호기와 보호기를 VHDL로 부호화하고 설계한 후, 관련 회로를 시뮬레이션한다. 또한 시뮬레이션된 회로를 XACT을 이용하여 XC 4025 FPGA에 실현하여 제안되 복호 알고리즘의 타당성을 확인한다.

FPGA Design of Modified Finite Field Divider Using Extended Binary GCD Algorithm (확장 이진 GCD 알고리듬을 이용한 개선된 유한체 나눗셈 연산기의 FPGA 설계)

  • Park, Ji-Won;Kang, Min-Sup
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.11a
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    • pp.925-927
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    • 2011
  • 본 논문에서는 확장 이진 최대공약수 알고리듬 (Extended Binary GCD algorithm)을 기본으로 GF($2^m$) 상에서 유한체 나눗셈 연산을 위한 고속 알고리듬을 제안하고, 제안한 알고리듬을 기본으로 한 나눗셈 연산기의 FPGA 설계 구현에 관하여 기술한다. 제안한 알고리듬은 Verilog HDL 로 기술하였고, Xilinx FPGA virtex4-xc4vlx15 디바이스를 타겟으로 하였다.

Implementation for Hardware IP of Real-time Face Detection System (실시간 얼굴 검출 시스템의 하드웨어 IP 구현)

  • Jang, Jun-Young;Yook, Ji-Hong;Jo, Ho-Sang;Kang, Bong-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2365-2373
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    • 2011
  • This paper propose the hardware IP of real-time face detection system for mobile devices and digital cameras required for high speed, smaller size and lower power. The proposed face detection system is robust against illumination changes, face size, and various face angles as the main cause of the face detection performance. Input image is transformed to LBP(Local Binary Pattern) image to obtain face characteristics robust against illumination changes, and detected the face using face feature data that was adopted to learn and generate in the various face angles using the Adaboost algorithm. The proposed face detection system can be detected maximum 36 faces at the input image size of QVGA($320{\times}240$), and designed by Verilog-HDL. Also, it was verified hardware implementation by using Virtex5 XC5VLX330 FPGA board and HD CMOS image sensor(CIS) for FPGA verification.

Implementation of a Real-time Multipath Fading Channel Simulator Using a Hybrid DSP-FPGA Architecture (DSP-FPGA 구조를 갖는 다중경로 페이딩 채널 시뮬레이터 구현)

  • 이주현;이찬길
    • The Journal of the Acoustical Society of Korea
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    • v.23 no.1
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    • pp.17-23
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    • 2004
  • The mobile radio channel can be simulated as a complex-valued random process with narrow-band spectrum. This paper describes a real-time implementation of that process using a INS320C6414 digital signal processor and XC2VP30 Virtex FPGA. The simulator presented here is not only a comprehensive model of the flat fading but also frequency selective fading mobile channel conditions. To replicate the statistical characteristics of the multipath fading environment with the minimum computational burden, multi-rate techniques are employed to resolve practical problems such as variable sampling rate. The simulator produces accurate and consistent results due to digital implementation. It is very flexible and simple to program for various field conditions in mobile communications with a graphical user interface.

Management of Citrus Canker in Argentina, a Success Story

  • Canteros, B.I.;Gochez, A.M.;Moschini, R.C.
    • The Plant Pathology Journal
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    • v.33 no.5
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    • pp.441-449
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    • 2017
  • Citrus canker is an important bacterial disease of citrus in several regions of the world. Strains of Xanthomonas citri type-A (Xc-A) group are the primary pathogen where citrus canker occurs. After Xc-A entered the Northeast of Argentina in 1974, the disease spread rapidly from 1977 to 1980 and then slowed down and remained moving at slow pace until 1990 when it became endemic. Citrus canker was detected in Northwest Argentina in 2002. This paper presents the main steps in the fight of the disease and the management strategies that have been used to control citrus canker at this time. We think the process might be usefull to other countries with the same situation. Results from more than 40 years of research in Northeast (NE) Argentina indicate that we are at the limit of favorable environment for the disease. The severity of citrus canker is greatly affected by the environment and El $Ni{\tilde{n}}o$ Southern Oscillation (ENSO) phenomenon which causes cyclic fluctuations on the disease intensity in the NE region. Weather-based logistic regression models adjusted to quantify disease levels in field conditions showed that the environmental effect was strongly modulated by the distance from a windbreak. Production of healthy fruits in citrus canker endemic areas is possible knowing the dynamics of the disease. A voluntary Integrated Plan to Reduce the Risk of Canker has been in place since 1994 and it allows growers to export unsymptomatic, uninfested fresh fruit to countries which are free of the disease and require healthy, pathogen free fruits. The experience from Argentina can be replicated in other countries after appropriate trials.

Design of General Peripheral Interface Using Serial Link (직렬 링크 방식의 주변 장치 통합 인터페이스 설계)

  • Kim, Do-Seok;Chung, Hoon-Ju;Lee, Yong-Hwan
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.1
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    • pp.68-75
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    • 2011
  • The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

Hardware Architecture Design and Implementation of IPM-based Curved Lane Detector (IPM기반 곡선 차선 검출기 하드웨어 구조 설계 및 구현)

  • Son, Haengseon;Lee, Seonyoung;Min, Kyoungwon;Seo, Sungjin
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.10 no.4
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    • pp.304-310
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    • 2017
  • In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

A Realtime Hardware Design for Face Detection (얼굴인식을 위한 실시간 하드웨어 설계)

  • Suh, Ki-Bum;Cha, Sun-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.397-404
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    • 2013
  • This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.

Region of Interest Extraction Method and Hardware Implementation of Matrix Pattern Image (매트릭스 패턴 영상의 관심 영역 추출 방법 및 하드웨어 구현)

  • Cho, Hosang;Kim, Geun-Jun;Kang, Bongsoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.4
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    • pp.940-947
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    • 2015
  • This paper presents the region of interest pattern image extraction method on a display printed matrix pattern. Proposed method can not use conventional method such as laser, ultrasonic waves and touch sensor. It searches feature point and rotation angle using luminance and pattern reliable feature points of input image, and then it extracts region of interest. In order to extract region of interest, we simulate proposed method using pattern image written various angles on display panel. The proposed method makes progress using the OpenCV and the window program, and was designed using Verilog-HDL and was verified through the FPGA Board(xc6vlx760) of Xilinx.