• Bulletin of the Korean Chemical Society
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• v.18 no.2
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• pp.193-197
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• 1997

Theoretical studies on the base-catalyzed deprotonation of 4-phenacylpyridinium cations, R1-CO-CH2-C5H4N-R2, I (R1=YC6H4 -and R2=CH3), and II (R1=C6H5 and R2=CH2C6H4Y) have been carried out with bases, NH3 and XC6H4NH2 using AM1 MO method. The Brψnsted α values are 0.20 and 0.22 and the βB values are 0.62 and 0.61, respectively for cations I and II. The negative Ⅰ (=α-βB) values obtained are in accord with the experimental results in aqueous solution, although the theoretical gas-phase α values for I are somewhat smaller than the experimental values in water due to neglect of solvation effect. It has been stressed that the Brψnsted α is distorted not only by the lag in the resonance and solvation development in the carbanion, but also by the difference in the distance between the anionic center and substituents in the TS and in the product anion.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.3
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• pp.79-94
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• 1998

본 논문에서는 컴퓨터 시스템에서 정보보호를 위해 가장 많이 사용하고 있는 DES(Data Encryption Standard)암호알고리즘을 시스템 설계 기술언어인 VHDL(Vhsic Hardware Description Language)로 설계하고 이것을 칩으로 합성하여 하드웨어에서 차지하는 면적과 속도를 비교 분석하였다. 설계방법에 있어서는 구현하는 방법에 따라 전 라운드 구현형, S-box 공유형 그리고 단일 라운드 반복형 범용성을 갖도록 하여 FPGA로 구현한다. 본 논문에서 구현한 단일 라운드 반복형 설계는 Synopsys의 EDA 툴을 이용하여 시뮬레이션 및 합성을 하였고, Xilinx사의 xdm을 이용하여 XC4052XL 칩에 구현하였다. 그 결과 입력 클록 50MHz상에서 100Mbps의 암,복호화 속도를 갖는 범용성 암호칩을 설계 및 구현한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.4
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• pp.21-32
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• 1998

통신 및 컴퓨터 시스템의 처리 속도가 높아짐에 따라 정보 보호를 위해서 고속의 데이터처리가 반드시 요구되어진다. 따라서 본 논문에서는 국제 표준 암호알로기즘의 하나인ISDEA(International Data Encryption Algorithm)를 고속 연산을 위하여 알고리즘을 분석하고 암호화 수행시간을 감소하기 위하여 파이프라인 처리를 하며, 서브키 생성시의 연산회수를 줄이기 위하여 서브키 블록을 EEPROM 으로 구현하였다. 전체적인 시스템은 VHDL(VHSIC Hardware Description Language)을 사용하여 설계하였다. IDEA 알고리듬은 EDA tool인 Synopsys를 사용하여 Sunthesis하였으며, Xilinx의 FPGA XC4052XL을 이용하여 One CHip화 시켰다. 입력 클럭으로 20Mhz를 사용하였을 때, data arrival time은 687.07ns였으며, 109.01 Mbp의 속도로 동작하 였다.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Clean Technology
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• v.19 no.3
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• pp.320-326
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• 2013

Nano-sized PtRu-Ni/VC and PtRu-Sn/VC electrocatalysts were synthesized by a one-step radiation-induced reduction (RIR) (30 kGy) process using distilled water as the solvent and Vulcan XC-72 as the supporting material. The obtained electrocatalysts were characterized by transmission electron microscopy (TEM), scanning electron microscope energy dispersive spectroscopic (SEM-EDS), X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), respectively. The catalytic efficiency of electrocatalysts was examined for oxygen reduction, MeOH oxidation and CO stripping decreased in the following order, Hydrogen stripping : PtRu-Sn/VC > PtRu-Ni/VC > PtRu/VC$^{(R)}$ (E-TEK). MeOH oxidation : PtRu-Sn/VC > PtRu-Ni/VC > PtRu/ VC$^{(R)}$ (E-TEK). Unit cell performance : PtRu-Sn/VC > PtRu-Ni/VC > PtRu/VC$^{(R)}$ (E-TEK) catalysts.

• Transactions of the Korean hydrogen and new energy society
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• v.26 no.2
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• pp.170-178
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• 2015

In this study, we carry out a study on how to improve performance of vanadium redox flow battery (VRFB) through promoting reaction rate of rate determining vanadium reaction ($[VO]^{2+}/[VO_2]^+$). In order to do that, three different carbons like Vulcan (XC-72), CMK3 and MSU-F-C are adopted as the catalysts, while their catalytic activity and reaction reversibility are evaluated using half-cell tests. Their topological images are also measured by TEM. For estimation of the VRFB performance, multiple charge-discharge curves of VRFBs including the catalysts are measured by single cell tests. As a result of that, MSU-F-C shows relatively excellent catalytic activity and reaction reversibility as well as large surface area compared to those of Vulcan (XC-72) and CMK3. Also, in terms of the performance of VRFBs including the catalysts, VRFB including MSU-F-C indicates (i) low charging/discharging overpotentials and low internal resistance, (ii) high charge/discharge capacities and (iii) high energy efficiency. These VRFB performance data are well agreed with results on catalytic activity and reaction reversibility. The reason that MSU-F-C induces superior VRFB performances is attributed to (i) its large surface area and (ii) its hydrophilic surface functional groups that mainly consist of hydroxyl bonds that are supposed to play active surface site role for facilitaing $[VO]^{2+}/[VO_2]^+$ redox reaction. Based on the above results, it is found that adoption of MSU-F-C as catalyst for VRFB results in improvement in VRFB performance by promoting the languid $[VO]^{2+}/[VO_2]^+$ redox reaction.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.1
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• pp.88-95
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• 2009

This paper presents a traffic pattern matching hardware that can be used in high performance network applications. The presented hardware is designed for a contents security system which is to block various kinds of information drain or intrusion activities. The hardware consists of two parts: the header lookup and string pattern matching parts. For implementing the header lookup part in hardware, the TCAMs(ternary CAMs) are popularly used. Since the TCAM approach is inefficient in terms of the hardware and memory costs and the power consumption, however, we adopt and modify an alternative approach based on the comparator arrays and the HiCuts tree. Our implementation results, using Xilinx FPGA XC4VSX55, show that our design can reduce the usage of the FPGA slices by about 26%, and the Block RAM by about 58%. In the design of string pattern matching part, we design and use a hashing module based on cellular automata, which is hardware efficient and consumes less power by adaptively changing its configuration to reduce the collision rates.

• Journal of IKEEE
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• v.24 no.1
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• pp.25-32
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• 2020

In this paper, we propose an image generator for OLED panel test that can compensate for color coordinates and luminance by using panel defect inspection and optical measurement while displaying images on OLED panel. The proposed image generator consists of two processes: the image generation process and the process of compensating color coordinates and luminance using optical measurement. In the image generating process, the panel is set to receive the panel information to drive the panel, and the image is output by adjusting the output setting of the image generator according to the panel information. The output form of the image is configured by digital RGB method. The pattern generation algorithm inside the image generator outputs color and gray image data by transmitting color data to a 24-bit data line based on a synchronization signal according to the resolution of the panel. The process of compensating color coordinates and luminance using optical measurement outputs an image to an OLED panel in an image generator, and compensates for a portion where color coordinates and luminance data measured by an optical module differ from reference data. To evaluate the accuracy of the image generator for the OLED panel test proposed in this paper, Xilinx's Spartan 6 series XC6SLX25-FG484 FPGA was used and the design tool was ISE 14.5. The output of the image generation process was confirmed that the target setting value and the simulation result value for the digital RGB output using the oscilloscope matched. Compensating the color coordinates and luminance using optical measurements showed accuracy within the error rate suggested by the panel manufacturer.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.