• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.521-531
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• 2009

Flash memory has physical characteristics different from hard disk where two costs of a read and write operations differ each other and an overwrite on flash memory is impossible to be done. In order to solve these restrictions with software, storage systems equipped with flash memory deploy FTL(Flash Translation Layer) software. Several FTL algorithms have been suggested so far and most of them prefer sequential write pattern to random write pattern. In this paper, we provide a new technique to efficiently store and maintain the B-tree index on flash memory. The operations like inserts, deletes, updates of keys for the B-tree generate random writes rather than sequential writes on flash memory, leading to inefficiency to the B-tree maintenance. In our technique, we convert random writes generated by the B-tree into sequential writes and then store them to the write-buffer on flash memory. If the buffer is full later, some sequential writes in the buffer will be issued to FTL. Our diverse experimental results show that our technique outperforms the existing ones with respect to the I/O cost of flash memory.

• Journal of Magnetics
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• v.6 no.4
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• pp.109-118
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• 2001

A computer simulation, utilizing the Landau-Lifshitz-Gilbert equation, of ultra-high- density recording on continuous longitudinal media is carried out. The two important features of this work are the use of a planar-type head, which enables a high write field of 14183 Oe ts be generated at the center of the recording medium, and the media with very high coercivities up to 13010 Oe. From a systematic investigation, it is found that the optimum write field is higher than the medium coercivity by only 3400 Oe over a wide coercivity range. This new finding allows one to write an a medium with a very high coercivity by using a planar-type head. It is demonstrated that a reasonably good bit pattern with a bit density of 605 kfci is generated on the medium with a coercivity of l1720 Oe, and, combined with a high track pitch density of 100 ktpi, a recording density of 60 Gb/in$^2$can be obtained in a single layer medium. With an improved write- head designs even a higher recording density of 75 Gb/in$^2$may be possible since comparison of the results for the bit pattern from the present head profile and the ideal Lindholm profile indicates an increase in the track pitch density of about 27%. Even at this density, the thermal stability parameter (KV/kT) at room temperature is high enough (60) to provide ample room for thermal stability.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.4
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• pp.134-139
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• 2008

A spirally arrayed nano-pattern is designed as a model pattern for the next generation optical storage media. The pattern consists off types of embossed rectangular dot, which are 50nm, 100nm, 150nm and 200nm in length and 50nm in width. The height of the dot is designed to be 50nm. The pitch of the spiral track of the pattern is 100nm. A ER(Electron resist) master for this pattern is fabricated by e-beam lithography process. The ER is first spin-coated to be 50nm thick on a Si wafer and then the model pattern is written on the coated ER layer by e-beam. After developing this pattern written wafer in the solution, a ER pattern master is fabricated. The most conventional e-beam machine can write patterns in orthogonal way, so we made our own pattern generator which can write the pattern in circular or spiral way. This program generates the patterns to be compatible with the e-beam machine from Raith(Raith 150). To fabricate 50nm pattern master precisely, a series of experiments were done including the design compensation for the pattern size, optimization of the dose, acceleration voltage, aperture size and developing. Through these experiments, we conclude that the higher accelerating voltages and smaller aperture size are better for mastering the nano pattern which is in order of 50nm. With the optimized e-beam lithography process, a spiral arrayed 50nm pattern master adopting PMMA resist was fabricated to have dimensional accuracy over 95% compared to the designed. Using this pattern master, a metal pattern stamp will be fabricated by Ni electro plating for injection molding of the patterned plastic substrate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.23-25
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• 1996

In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.193-194
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• 2013

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.132-134
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• 1994

In this study, the gnenral purpose type Linear Pulse Motor(LPM) and measurement system were desisted. And this LPM is tested by the experimental apparatus to write up a operating pattern parameter.