• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2828-2835
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• 1996

In this paper we propose a new shaping algorithm which can control the shaping delay and the output buffer size based on the leaky bucket counter with a threshold value. This paper assumes that input traffic of the proposed shaping algorithm is the worst case traffic tolerated by the continuous leaky bucket algorithm and claracterizes traffic patterns that can depart from our shaping algorithm. We also compare shaping delay and output buffer size of the proposed algorithm with the existing shaping algorithm without a threshold value. Our results show that the proposed shaping algorithm can easily manage the shaping delay and output buffer size than any other mechanism.

• The Journal of Asian Finance, Economics and Business
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• v.7 no.11
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• pp.843-851
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• 2020

This study focuses on identifying and prioritizing the broader performance measures for the service supply chains by taking the case of Majan Electricity Company, Sohar, in the Sultanate of Oman. For an examination of the uniformity of ultimate objectives and the priorities therein, two strata of respondents with a total of fourteen respondents were approached for their valuable insights. Suitable structured instruments were personally administered to elicit the insightful and worthy responses. The two multi-criteria decision-making techniques, namely, the Fuzzy Analytical Hierarchy Process and the Best-Worst Method were used to reach a meaningful prioritization of the identified and refined broader performance measurement dimensions. The results show that there exists a minor gap between the two respondents' groups in terms of their prioritizations. The major finding points to the difference in terms of the topmost priorities as revealed by the two set of respondents. For one group of respondents, the customer satisfaction matters the most, whereas for the other group, it is the overall profitability that matters the most. This gap against the utopian state assists in concluding that there is a requirement to reorient the employees so as to have a shared and common understanding of the organizational priorities.

• Journal of the Korean Institute of Gas
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• v.24 no.6
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• pp.83-90
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• 2020

This study conducted a risk assessment using the HyKoRAM program created by international joint research. Risk assessment was conducted based on accident scenarios and worst-case scenarios that could occur in the facility, reflecting design specifications of major facilities and components such as compressors, storage tanks, and hydrogen pipes in the hydrogen charging station, and environmental conditions around the demonstration complex. By identifying potential risks of hydrogen charging stations, we are going to derive the worst leakage, fire, explosion, and accident scenarios that can occur in hydrogen storage tanks, treatment facilities, storage facilities, and analyze the possibility of accidents and the effects of damage on human bodies and surrounding facilities to review safety.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.3 no.1 s.4
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• pp.13-19
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• 2004

The VCO(Voltage Controlled Oscillator) with low phase noise and high reliability is implemented using nonlinear design, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise, and the qualify factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCO. The developed VCO has the oscillating tuning factor of 0.56MHz/V for the control voltage range of 0$\~$12V This VCO requires the DC power of 160mW. The phase noise characteristics exhibit good performances of -96.51dBc/Hz @ 10KHz and -116.3dBc/Hz @ 100KHz, respectively. And, the output power of 7.33 dBm is measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.2
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• pp.251-256
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• 2001

An error probability analysis is performed far a hybrid DS/SFH spread-spectrum system using minimum shift keying(MSK) modulation. The channel is assumed to be a Rayleigh fading channel with partial-band noise interference. Expressions are derived for the bit error rate(BER) in the context of Rician and Rayleigh fading channels, as a function of the average signal-to-noise ratio(SNR) $E_b/N_0$, the average signal-to- interference ratio(SJR) $E_b/N_J$, and channel parameters. As a result, in the fading channel with large Rician factor, K, which denotes the ratio of power of the direct and the diffused components, the partial-band interference is the worst case. On the other hand, in Rayleigh fading channel(K=0), the full-band interference($\rho$=1) brings the system to the worst case. Performance comparisons among various channels show that the factor K has much large effect on overall performance. For example, in conditions of $\rho$=0.1 and BER=$10^-2$, the system in Rician channel with K=10 requires more 1.9 dB SNR than that in AWGN channel, whereas it is less 5 dB SNR than that in the Rayleigh channel with K=0.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.408-414
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• 2005

The VCDRO(Voltage Controlled Dielectric Resonate. Oscillator) with low phase noise is designed using nonlinear analysis, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise performance, and the quality factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCDRO and the reliability analysis is accomplished to estimate the probability of operation at the end of life. The developed VCDRO has the oscillating tuning factor of 0.56MHZ1V for the control voltage range of 0-l2V. This VCDRO requires the DC power of 136mW. The phase noise characteristics exhibit good performances of -94.18dBc/Hz (a)10KHz and -116.3dBc/Hz (a)100KHz. And, the output power over 7.33dBm is measured.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.963-969
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• 2000

In this paper, we define two input-output gains of linear periodic time-varying systems. One is the ratio of output with worst-case l2-norm over all inputs with unit 12-norm. It denotes G($\iota_2,\iota_2$.The other is the ratio of output with worst-case RMS value over all inputs with unit RMS value. It denotes G(RMS, RMS) .It is fact that these two gains are equivalent for linear time-invariant system. In this paper, we prove these two gains are also equivalent for linear periodic time-varying system. In addition, the relationship between two method of obtaining the generalized frequency responses for linear periodic time-varying system is derived. Finally, we apply the defined input-output gains to M-channel filter-bank which is multi-rate signal Processing system, used to speech coding. In the filter-bank, generally, aliasing distortion, magnitude distortion, and phase distortion are present. It is shown that these are kept small if the filter-bank is designed by a method that optimizes the gain G($\iota_2,\iota_2$ of an error system.

• Journal of Korea Multimedia Society
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• v.16 no.12
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• pp.1427-1438
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• 2013

We have developed a 128-bit stream cipher algorithm composed of the 5-stage pipeline, capable of real-time processing, confidentiality and integrity. The developed stream cipher is a stream cipher algorithm that makes the final 128-bit ciphers through a whitening process after making the ASR 277 bit and SHACAL-2 and applying them to the CFB mode. We have verified the hardware performance of the proposed stream cipher algorithm with Modelsim 6.5d and Quartus II 12.0, and the result shows that the hardware runs at 33.34Mhz(4.27Gbps) at worst case. According to the result, the new cipher algorithm has fully satisfied the speed requirement of wireless Internet and sensor networks, and DRM environment. Therefore, the proposed algorithm with satisfaction of both confidentiality and integrity provides a very useful ideas.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.70-84
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• 2006

We propose a new distributed QoS routing scheme called pre-computation based selective probing (PCSP). The PCSP scheme is designed to provide an exact solution to the constrained optimization problem with moderate overhead, considering the practical environment where the state information available for the routing decision is not exact. It does not limit the number of probe messages, instead, employs a qualitative (or conditional) selective probing approach. It considers both the cost and QoS metrics of the least-cost and the best-QoS paths to calculate the end-to-end cost of the found feasible paths and find QoS-satisfying least-cost paths. It defines strict probing condition that excludes not only the non-feasible paths but also the non-optimal paths. It additionally pre-computes the QoS variation taking into account the impreciseness of the state information and applies two modified QoS-satisfying conditions to the selection rules. This strict probing condition and carefully designed probing approaches enable to strictly limit the set of neighbor nodes involved in the probing process, thereby reducing the message overhead without sacrificing the optimal properties. However, the PCSP scheme may suffer from high message overhead due to its conservative search process in the worst case. In order to bound such message overhead, we extend the PCSP algorithm by applying additional quantitative heuristics. Computer simulations reveal that the PCSP scheme reduces message overhead and possesses ideal success ratio with guaranteed optimal search. In addition, the quantitative extensions of the PCSP scheme turn out to bound the worst-case message overhead with slight performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.