• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.26-32
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• 2008

The performance of an analog winner-take-all(WTA) circuit is affected by the corner error and the offset error. Despite the fact that the corner error can be reduced with large transconductance of the transistor, the offset error caused by device mismatch has not been completely studied. This paper presents the complete offset error analysis, and proposes low offset design guidelines and an offset cancellation scheme. The experimental results show good agreement with the theoretical analysis and the drastic improvement of the offset error.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.55-60
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• 2007

This paper presents a compact double resolution scheme for the optical angle sensor based on 1-dimensional CMOS photodiode pixel array. All the pixels are divided into the even pixel and the odd pixel groups. The winner take all circuit is provided for each group. The proposed interpolation scheme increases the resolution by 2 from the winner addresses and winner values. The interpolation scheme can be implemented without any additional pixels or winner take all circuits and require only a comparator and a XOR gate. The proposed pixel array chip that has 336 photodiode pixels with $5.6{\mu}m$ pitch was fabricated with $0.35{\mu}m$ CMOS process and was assembled with a $50{\mu}m$ slit to form an angle sensor. The measured resolution is $0.1{\circ}$ with the proposed interpolation. The chip consumes 35mW and provides 8k samples per second.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1386-1389
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• 2002

We consider interleaved buck converters using a switching rule based on Winner-Take-All (ab. WTA) nonlinearity. We clarify that this system exhibits various bifurcation phenomena. We also show that the switching phase of each converter is controlled by the WTA. Using a simple test circuit, ripple reduction and typical phenomena are verified in the laboratory.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.2
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• pp.87-92
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• 2001

This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.357-364
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• 2015

This research presents a DC-DC converter controller implemented with an analog memory. The structure of the converter will contribute to solve the stability problem unavoidable in a conventional closed loop converter. The analog memory will be used for realizing CAM(Contents Addressable Memory) which contains the output of the converter and the relevant duty ratio, respectively. The operation for reading in the memory is executed with an absolute differencing circuit and a WTA(Winner-Take-All) circuit suitable for a nearest-match function of the CAM. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.2
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• pp.102-106
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• 2003

This paper describes a new pattern classifier neural network to extract the feature from a letter. The proposed pattern classifier is based on relative distance, which is measure between an input datum and the center of cluster group. So, the proposed classifier neural network is called relative neural network(RNN). According to definitions of the distance and the learning rule, the structure of RNN is designed and the pseudo code of the algorithm is described. In feature extraction of letter, RNN, in spite of deletion of learning rate, resulted in the identical performance with those of winner-take-all(WTA), and self-organizing-map(SOM) neural network. Thus, it is shown that RNN is suitable to extract the feature of a letter.