• Atmosphere
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• v.33 no.4
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• pp.423-440
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• 2023

The updated version of Global Ocean Data Assimilation and Prediction System (GODAPS) in the NIMS/KMA (National Institute of Meteorological Sciences/Korea Meteorological Administration), which has been in operation since December 2021, is being introduced. This technical note on GODAPS2 describes main progress and updates to the previous version of GODAPS, a software tool for the operating system, and its improvements. GODAPS2 is based on Forecasting Ocean Assimilation Model (FOAM) vn14.1, instead of previous version, FOAM vn13. The southern limit of the model domain has been extended from 77°S to 85°S, allowing the modelling of the circulation under ice shelves in Antarctica. The adoption of non-linear free surface and variable volume layers, the update of vertical mixing parameterization, and the adjustment of isopycnal diffusion coefficient for the ocean model decrease the model biases. For the sea-ice model, four vertical ice layers and an additional snow layer on top of the ice layers are being used instead of previous single ice and snow layers. The changes for data assimilation include the updated treatment for background error covariance, a newly added bias scheme combined with observation bias, the application of a new bias correction for sea level anomaly, an extension of the assimilation window from 1 day to 2 days, and separate assimilations for ocean and sea-ice. For comparison, we present the difference between GODAPS and GODAPS2. The verification results show that GODAPS2 yields an overall improved simulation compared to GODAPS.

• Journal of the Korean Vacuum Society
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• v.18 no.4
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• pp.302-309
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• 2009

We fabricated a Si nano floating gate memory with Schottky barrier tunneling transistor structure. The device was consisted of Schottky barriers of Er-silicide at source/drain and Si nanoclusters in the gate stack formed by LPCVD-digital gas feeding method. Transistor operations due to the Schottky barrier tunneling were observed under small gate bias < 2V. The nonvolatile memory properties were investigated by measuring the threshold voltage shift along the gate bias voltage and time. We obtained the 10/50 mseconds for write/erase times and the memory window of $\sim5V$ under ${\pm}20\;V$ write/erase voltages. However, the memory window decreased to 0.4V after 104seconds, which was attributed to the Er-related defects in the tunneling oxide layer. Good write/erase endurance was maintained until $10^3$ write/erase times. However, the threshold voltages moved upward, and the memory window became small after more write/erase operations. Defects in the LPCVD control oxide were discussed for the endurance results. The experimental results point to the possibility of a Si nano floating gate memory with Schottky barrier tunneling transistor structure for Si nanoscale nonvolatile memory device.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.2
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• pp.31-43
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• 2000

This paper presents a novel algorithm lot extraction of the eye and mouth fields (facial features) from 2D gray level face images. First of all, it has been found that Eigenfeatures, derived from the eigenvalues and the eigenvectors of the binary edge data set constructed from the eye and mouth fields are very good features to locate these fields. The Eigenfeatures, extracted from the positive and negative training samples for the facial features, ate used to train a MultiLayer Perceptron(MLP) whose output indicates the degree to which a particular image window contains the eye or the mouth within itself. Second, to ensure robustness, the ensemble network consisting of multiple MLPs is used instead of a single MLP. The output of the ensemble network becomes the average of the multiple locations of the field each found by the constituent MLPs. Finally, in order to reduce the computation time, we extracted the coarse search region lot eyes and mouth by using prior information on face images. The advantages of the proposed approach includes that only a small number of frontal faces are sufficient to train the nets and furthermore, lends themselves to good generalization to non-frontal poses and even to other people's faces. It was also experimentally verified that the proposed algorithm is robust against slight variations of facial size and pose due to the generalization characteristics of neural networks.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.79-89
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• 2006

TCP is the most widely used transport protocol in Internet applications that guarantees a reliable data transfer. But, in the wireless multi-hop networks, TCP performance is degraded because it is designed for wired networks. The main reasons of TCP performance degradation are contention for wireless medium at the MAC layer, hidden terminal problem, exposed terminal problem, packet losses in the link layer, unfairness problem, reordering problem caused by path disconnection, bandwidth waste caused by exponential backoff of retransmission timer due to node's mobility and so on. Specially, in the mobile ad-hoc networks, discrepancy between a station's transmission range and interference range produces hidden terminal problem that decreases TCP performance greatly by limiting simultaneous transmission at a time. In this paper, we propose a new MAC algorithm for mobile ad-hoc networks to solve the problem that a node can not transmit and just increase CW by hidden terminal. In the IEEE 802.11 MAC DCF, a node increases CW exponentially when it fails to transmit, but the proposed algorithm, changes CW adaptively according to the reason of failure so we get a TCP performance enhancement. We show by ns-2 simulation that the proposed algorithm enhances the TCP performance by fairly distributing the transmission opportunity to the failed nodes by hidden terminal problems.

• Applied Chemistry for Engineering
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• v.31 no.3
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• pp.291-298
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• 2020

ZITO/Ag/ZITO multilayer transparent electrodes at room temperature on glass substrates were prepared using RF/DC magnetron sputtering. Transparent conductive films with a sheet resistance of 9.4 Ω/㎡ and a transmittance of 83.2% at 550 nm were obtained for the multilayer structure comprising ZITO/Ag/ZITO (100/8/42 nm). The sheet resistance and transmittance of ZITO/Ag/ZITO multilayer films meant that they would be highly applicable for use in polymer-dispersed liquid crystal (PDLC)-based smart windows due to the ability to effectively block infrared rays (heat rays) and thereby act as an energy-saving smart glass. Effects of the thickness of the PDLC layer and the intensity of ultraviolet light (UV) on electro-optical properties, photopolymerization kinetics, and morphologies of difunctional urethane acrylate-based PDLC systems were investigated using new transparent conducting electrodes. A PDLC cell photo-cured using UV at an intensity of 2.0 mW/c㎡ with a 15 ㎛-thick PDLC layer showed outstanding off-state opacity, good on-state transmittance, and favorable driving voltage. Also, the PDLC-based smart window optimized in this study formed liquid crystal droplets with a favorable microstructure, having an average size range of 2~5 ㎛ for scattering light efficiently, which could contribute to its superior final performance.

• Korean Journal of Materials Research
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• v.30 no.10
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• pp.509-514
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• 2020

The two key variables of an Si solar cell, i.e., emitter (n-type window layer) and base (p-type substrate) doping levels or concentrations, are studied using Medici, a 2-dimensional semiconductor device simulation tool. The substrate is p-type and 150 ㎛ thick, the pn junction is 2 ㎛ from the front surface, and the cell is lit on the front surface. The doping concentration ranges from 1 × 10¹⁰ cm^-3 to 1 × 10²⁰ cm^-3 for both emitter and base, resulting in a matrix of 11 by 11 or a total of 121 data points. With respect to increasing donor concentration (Nd) in the emitter, the open-circuit voltage (Voc) is little affected throughout, and the short-circuit current (Isc) is affected only at a very high levels of Nd, exceeding 1 × 10¹⁹ cm^-3, dropping abruptly by about 12%, i.e., from Isc = 6.05 × 10^-9 A·㎛^-1, at Nd = 1 × 10¹⁹ cm^-3 to Isc = 5.35 × 10^-9 A·㎛^-1 at Nd = 1 × 10²⁰ cm^-3, likely due to minority-carrier, or hole, recombination at the very high doping level. With respect to increasing acceptor concentration (Na) in the base, Isc is little affected throughout, but Voc increases steadily, i.e, from Voc = 0.29 V at Na = 1 × 10¹² cm^-3 to 0.69 V at Na = 1 × 10¹⁸ cm^-3. On average, with an order increase in Na, Voc increases by about 0.07 V, likely due to narrowing of the depletion layer and lowering of the carrier recombination at the pn junction. At the maximum output power (Pmax), a peak value of 3.25 × 10^-2 W·cm^-2 or 32.5 mW·cm^-2 is observed at the doping combination of Nd = 1 × 10¹⁹ cm^-3, a level at which Si is degenerate (being metal-like), and Na = 1 × 10¹⁷ cm^-3, and minimum values of near zero are observed at very low levels of Nd ≤ 1 × 10¹³ cm^-3. This wide variation in Pmax, even within a given kind of solar cell, indicates that selecting an optimal combination of donor and acceptor doping concentrations is likely most important in solar cell engineering.

• Journal of the Korean Solar Energy Society
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• v.32 no.4
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• pp.24-33
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• 2012

Recently, finishing materials at spandrel area, a part of curtain-wall system, are gradually forced to improve thermal insulation performance in order to enhance the building energy efficiency. Also, Building Integrated Photovoltaics(BIPV) systems have been installed in the exterior side of the spandrel area, which is generally composed of windows. Those BIPVs aim to achieve high building energy efficiency and supply the electricity to building. However, if transparent BIPV module is combined with high insulated spandrel, it would reduce the PV efficiency for two major reasons. First, temperature in the air space, located between window layer and finishing layer of the spandrel area, can significantly increase by solar heat gain, because the space has a few air density relative to other spaces in building. Secondly, PV has a characteristics of decreased Voltage(Voc and Vmp) with the increased temperature on the PV cell. For these reasons, this research analyzed a direct interrelation between PV Cell temperature and electricity generation performance under different insulation conditions in the spandrel area. The different insulation conditions under consideration are 1) high insulated spandrel(HIS) 2) low insulated spandrel(LIS) 3) PV stand alone on the ground(SAG). As a result, in case of 1) HIS, PV temperature was increased and thus electricity generation efficiency was decreased more than other cases. To be specific, each cases' maximum temperature indicated that 1) HIS is $83.8^{\circ}C$, 2) LIS is $74.2^{\circ}C$, and 3) SAG is $66.3^{\circ}C$. Also, each cases yield electricity generation like that 1) HIS is 913.3kWh/kWp, 2) LIS is 942.8kWh/kWp, and 3) SAG is 981.3kWh/kWp. These result showed that it is needed for us to seek to the way how the PV Cell temperature would be decreased.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.105-109
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• 2005

A compact antenna switch module for GSM/DCS dual band applications based on multilayer low temperature co-fired ceramic (LTCC) substrate is presented. Its size is $4.5{\times}3.2{\times}0.8 mm^3$ and insertion loss is lower than 1.0 dB at Rx mode and 1.2 dB at Tx mode. To verify the stability of the developed module to the process window, each block that is diplexer, LPF's and bias circuit is measured by probing method in the variation with the thickness of ceramic layer and the correlation between each block is quantified by calculating the VSWR In the mean while, two types of bias circuits -lumped and distributed - are compared. The measurement of each block and the calculation of VSWR give good information on the behavior of full module. The reaction of diplexer to the thickness is similar to those of LPF's and bias circuit, which means good relative matching and low value of VSWR, so total insertion loss is maintained in quite wide range of the thickness of ceramic layer at both band. And lumped type bias circuit has smaller insertion itself and better correspondence with other circuit than distributed stripline structure. Evaluated ceramic module adopting lumped type bias circuit has low insertion loss and wider stability region of thickness over than 6um and this can be suitable for the mass production. Stability characterization by probing method can be applied widely to the development of ceramic modules with embedded passives in them.