• 제목/요약/키워드: Window layer

검색결과 352건 처리시간 0.033초

Role of $N_2$ flow rate on etch characteristics and variation of line edge roughness during etching of silicon nitride with extreme ultra-violet resist pattern in dual-frequency $CH_2F_2/N_2$/Ar capacitively coupled plasmas

  • 권봉수;정창룡;이내응;이성권
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.458-458
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    • 2010
  • The process window for the etch selectivity of silicon nitride ($Si_3N_4$) layers to extreme ultra-violet (EUV) resist and variation of line edge roughness (LER) of EUV resist were investigated durin getching of $Si_3N_4$/EUV resist structure in a dual-frequency superimposed capacitive coupled plasma (DFS-CCP) etcher by varying the process parameters, such as the $CH_2F_2$ and $N_2$ gas flow rate in $CH_2F_2/N_2$/Ar plasma. The $CH_2F_2$ and $N_2$ flow rate was found to play a critical role in determining the process window for infinite etch selectivity of $Si_3N_4$/EUV resist, due to disproportionate changes in the degree of polymerization on $Si_3N_4$ and EUV resist surfaces. The preferential chemical reaction between hydrogen and carbon in the hydrofluorocarbon ($CH_xF_y$) polymer layer and the nitrogen and oxygen on the $Si_3N_4$, presumably leading to the formation of HCN, CO, and $CO_2$ etch by-products, results in a smaller steady-state hydrofluorocarbon thickness on $Si_3N_4$ and, in turn, in continuous $Si_3N_4$ etching due to enhanced $SiF_4$ formation, while the $CH_xF_y$ layer is deposited on the EUV resist surface. Also critical dimension (and line edge roughness) tend to decrease with increasing $N_2$ flow rate due to decreased degree of polymerization.

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CVD 그래핀을 이용한 저저항 투명면상발열 시스템 (Low-resistance Transparent Plane Heating System using CVD Graphene)

  • 유병욱;한상수
    • 한국정보전자통신기술학회논문지
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    • 제12권3호
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    • pp.218-223
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    • 2019
  • 높은 CVD 그래핀저항으로 인한 낮은 발열효과를 해결하기 위해 다층으로 그래핀을 적층하여, 저저항의 광학특성이 우수한 투명 면상 발열시스템을 구현하였다. 제작한 CVD 그래핀의 발열필름으로 $300{\times}400{\times}5mm$ 발열체를 제작하고, 효율적인 전력을 구동하기 위해 PWM 제어를 통한 회로를 구성하여 시스템을 구현하였다. 발열체로 사용한 4층의 CVD 그래핀 필름의 평균 면 저항 측정값은 $85.5{\Omega}/sq$이다. 따라서 저 저항의 CVD 그래핀의 구현 방법으로 열전사의 적층의 방법은 타당하다. 발열시험 결과, CVD 그래핀을 이용한 저저항 투명 면상 발열 시스템의 평균 발열상승은 $10^{\circ}C/min$ 이고, 86.44%의 CVD 그래핀 필름의 광투과율을 갖음을 보여준다. 따라서 제시한 발열 시스템은 대형창 유리 및 자동차 발열유리로서 적용가능하다.

Optical and electrical property of Indium-doped ZnO (IZO) grown by Atomic Layer Deposition (ALD) using Et2InN(TMS)2 as In precursor and H2O oxidant

  • 조영준;장효식
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.421.1-421.1
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    • 2016
  • We studied indium-doped zinc oxide (IZO) film grown by atomic layer deposition (ALD) as transparent conductive oxide (TCO). A variety of TCO layer, such as ZnO:Al (AZO), InSnO2(ITO), Zn (O,S) etc, has been grown by various method, such as ALD, chemical vapor deposition (CVD), sputtering, laser ablation, sol-gel technique, etc. Among many deposition methods, ALD has various advantages such as uniformity of film thickness, film composition, conformality, and low temperature deposition, as compared with other techniques. In this study, we deposited indium-doped zinc oxide thin films using diethyl[bis(trimethylsilyl)amido]indium [Et2InN(TMS)2] as indium precursor, DEZn as zinc precursor and H2O as oxidant for ALD and investigated the optical and electrical properties of IZO films. As an alternative, this liquid In precursor would has several advantages in indium oxide thin-film processes by ALD, especially for low resistance indium oxide thin film and high deposition rate as compared to InCp, InCl3, TMIn precursors etc. We found out that Indium oxide films grown by Et2InN(TMS)2 and H2O precursor show ALD growth mode and ALD growth window. We also found out the different growth rate of Indium oxide as the substrate and investigated the effect of the substrate on Indium oxide growth.

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TMS320C64x 기반 MPEG-1 LayerII Decoder의 DSP 구현 (Implementation of the MPEG-1 Layer II Decoder Using the TMS320C64x DSP Processor)

  • 조충상;이영한;오유리;김홍국
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.257-258
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    • 2006
  • In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

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Pt 나노입자와 Hybrid Pt-$SiO_2$ 나노입자의 합성과 활용 및 입자박막 제어 (Synthesis and application of Pt and hybrid Pt-$SiO_2$ nanoparticles and control of particles layer thickness)

  • 최병상
    • 한국전자통신학회논문지
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    • 제4권4호
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    • pp.301-305
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    • 2009
  • Pt 나노입자의 합성과 이를 이용한 hybrid Pt-$SiO_2$ 나노입자의 합성을 성공적으로 수행하였으며, self-assembled Pt nanoparticles monolayer를 charge trapping layer로 활용하는 metal-oxide-semiconductor(MOS) type memory의 한 예로 non-volatile memory(NVM)의 응용을 보임으로써 나노입자의 활용 가능성을 보이고, 또한, hybrid Pt-$SiO_2$ 나노입자 박막 층의 제어를 통한 MOS type memory device에의 보다 더 넓은 활용 가능성을 보이고자 하였다.

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플라즈마 ALD법에 의해 제조된 마이크로볼로미터용 바나듐 산화막의 제작 및 특성 (Fabrication and Properties of Vanadium Oxide Thin Films for Microbolometer by using Plasma Atomic Layer Deposition Method)

  • 윤형선;정순원;정상현;김광호;최창억;유병곤
    • 한국전기전자재료학회논문지
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    • 제21권2호
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    • pp.156-161
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    • 2008
  • The fabrication of vanadium oxide films directly on Si(100) substrates by plasma atomic layer deposition(ALD) with vanadium oxytriisopropoxide(VOIP) and oxygen as the reactants have been performed at temperature ranging from 250 to $450^{\circ}C$. Growth rate of vanadium oxide was $2.8{\AA}$/cycle at $300{\sim}400^{\circ}C$ defined as ALD acceptable temperature window, Vanadium oxide has been shown the different phases at $250^{\circ}C$ and more than $300^{\circ}C$. It has been confirmed that the phase of the films deposited at $250^{\circ}C\;was\;V_2O_5$ type and that of the films above $300^{\circ}C\;was\;VO_2(T)$ type measured at room temperature, respectively. A large change in resistance and small temperature hysteresis corresponding to a temperature has been observed in the vanadium oxide film deposited at temperature $350^{\circ}C$.

비진공 나노입자 코팅법을 이용한 CIGS 박막 태양전지 제조 (Fabrication of CIGS Thin Film Solar Cell by Non-Vacuum Nanoparticle Deposition Technique)

  • 안세진;김기현;윤경훈
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2006년도 춘계학술대회
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    • pp.222-224
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    • 2006
  • A non-vacuum process for $Cu(In,Ga)Se_2$ (CIGS) thin film solar cells from nanoparticle precursors was described in this work CIGS nanoparticle precursors was prepared by a low temperature colloidal route by reacting the starting materials $(CuI,\;InI_3,\;GaI_3\;and\;Na_2Se)$ in organic solvents, by which fine CIGS nanoparticles of about 20nm in diameter were obtained. The nanoparticle precursors were mixed with organic binder material for the rheology of the mixture to be adjusted for the doctor blade method. After depositing the mixture of CIGS with binder on Mo/glass substrate, the samples were preheated on the hot plate in air to evaporate remaining solvents ud to burn the organic binder material. Subsequently, the resultant (porous) CIGS/Mo/glass simple was selenized in a two-zone Rapid Thermal Process (RTP) furnace in order to get a solar ceil applicable dense CIGS absorber layer. Complete solar cell structure was obtained by depositing. The other layers including CdS buffer layer, ZnO window layer and Al electrodes by conventional methods. The resultant solar cell showed a conversion efficiency of 0.5%.

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Mechanical behavior test and analysis of HEH sandwich external wall panel

  • Wu, Xiangguo;Zhang, Xuesen;Tao, Xiaokun;Yang, Ming;Yu, Qun;Qiu, Faqiang
    • Advances in concrete construction
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    • 제13권 2호
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    • pp.153-162
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    • 2022
  • Prefabricated exterior wall panel is the main non-load-bearing component of assembly building, which affects the comprehensive performance of thermal insulation and durability of the building. It is of great significance to develop new prefabricated exterior wall panel with durable and lightweight characteristics for the development of energy-saving and assembly building. In the prefabricated sandwich insulation hanging wall panel, the selection of material for the outer layer and the arrangement of the connector of the inner and outer wall layers affect the mechanical performance and durability of the wall panels. In this paper, high performance cement-based composites (HPFRC) are used in the outer layer of the new type wall panel. FRP bars are used as the interface connector. Through experiments and analysis, the influence of the arrangement of connectors on the mechanical behaviors of thin-walled composite wall panel and the panel with window openings under two working conditions are investigated. The failure modes and the role of connectors of thin-walled composite wallboard are analyzed. The influence of the thickness of the wall layer and their combination on the strain growth of the control section, the initial crack resistance, the ultimate bearing capacity and the deformation of the wall panels are analyzed. The research work provides a technical reference for the engineering design of the light-weight thin-walled and durable composite sandwich wall panel.

Analysis of electrochemical double-layer capacitors using a Natural Rubber-Zn based polymer electrolyte

  • Nanditha Rajapaksha;Kumudu S. Perera;Kamal P. Vidanapathirana
    • Advances in Energy Research
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    • 제8권1호
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    • pp.41-57
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    • 2022
  • Electrochemical double-layer capacitors (EDLCs) based on solid polymer electrolytes (SPEs) have gained an immense recognition in the present world due to their unique properties. This study is about preparing and characterizing EDLCs using a natural rubber (NR) based SPE with natural graphite (NG) electrodes. NR electrolyte was consisted with 49% methyl grafted natural rubber (MG49) and zinc trifluoromethanesulfonate ((Zn(CF3SO3)2-ZnTF). It was characterized using electrochemical impedance spectroscopy (EIS) test, dc polarization test and linear sweep voltammetry (LSV) test. NG electrodes were made using a slurry of NG and acetone. EIS test, cyclic voltammetry (CV) test and galvanostatic charge discharge (GCD) test have been done to characterize the EDLC. Optimized electrolyte composition with NR: 0.6 ZnTF (weight basis) exhibited a conductivity of 0.6 x 10-4 Scm-1 at room temperature. Conductivity was predominantly due to ions. The electrochemical stability window was found to be from 0.25 V to 2.500 V. Electrolyte was sandwiched between two identical NG electrodes to fabricate an EDLC. Single electrode specific capacitance was about 2.26 Fg-1 whereas the single electrode discharge capacitance was about 1.17 Fg-1. The EDLC with this novel NR-ZnTF based SPE evidences its suitability to be used for different applications with further improvement.

이중계층구조 파티클 샘플링을 사용한 다중객체 검출 및 추적 (Multi-Object Detection and Tracking Using Dual-Layer Particle Sampling)

  • 정경원;김나현;이승원;백준기
    • 전자공학회논문지
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    • 제51권9호
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    • pp.139-147
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    • 2014
  • 본 논문에서는 다중객체 검출과 동시에 추적을 수행하는 이중계층구조의 파티클 샘플링을 제안한다. 제안된 방법은 다중 객체 검출을 위한 상위 계층 파티클 샘플링과 검출된 객체의 추적을 위한 하위 계층 파티클 샘플링으로 구성된다. 상위 계층에서는 빠른 객체 검출을 위해 슬라이딩 윈도우 대신 움직임 추정 기반의 부모 파티클 (parent particles; PP) 윈도우를 사용하여, 이동 객체 주위로 리샘플링된 파티클을 통해 객체를 검출한다. 하위 계층에서는 상위 계층에서 검출한 객체의 객체영역에 자식 파티클 (child particles; CP)을 생성하여 해당 객체를 추적한다. 실험결과를 통해 비디오 시스템에서 기존 객체 검출 방법보다 빠른 검출이 가능하고, 다중 객체를 효과적으로 추적할 수 있음을 확인하였다.