• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권8호
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• pp.2053-2067
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• 2023

This paper proposes two video quality assessment methods based on deep neural network. (i)The first method uses the IQF-CNN (convolution neural network based on image quality features) to build image quality assessment method. The LIVE image database is used to test this method, the experiment show that it is effective. Therefore, this method is extended to the video quality assessment. At first every image frame of video is predicted, next the relationship between different image frames are analyzed by the hysteresis function and different window function to improve the accuracy of video quality assessment. (ii)The second method proposes a video quality assessment method based on convolution neural network (CNN) and gated circular unit network (GRU). First, the spatial features of video frames are extracted using CNN network, next the temporal features of the video frame using GRU network. Finally the extracted temporal and spatial features are analyzed by full connection layer of CNN network to obtain the video quality assessment score. All the above proposed methods are verified on the video databases, and compared with other methods.

• 한국진공학회지
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• 제22권3호
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• pp.150-155
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• 2013

태양전지의 표면에 텍스쳐 구조를 형성하면 빛의 반사율을 줄일 수 있으므로 태양전지의 효율을 증가시킬 수 있다. 또한 표면의 텍스쳐 구조는 넓은 파장대역에서 빛의 반사를 줄여주기 때문에 다중접합 III-V화합물 태양전지에 아주 유용하다. 본 연구에서는 얇은 Pt층을 식각 마스크로 사용하여 다중접합 III-V태양전지의 window층으로 사용되는 InAlP층에 다양한 텍스쳐 구조를 형성하고 반사율을 측정하였다. 습식식각에 의해 나노미터 크기로 형성된 피라미드 꼴 텍스쳐 구조는 $0.3{\sim}1.5{\mu}m$의 넓은 파장영역에서 빛의 반사율을 13.7%까지 감소시켰다.

• 정보처리학회논문지D
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• 제8D권3호
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• pp.265-272
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• 2001

이동단말(mobile phone, PDA, smart phone, notebook PC 등)에서 WAP을 구현하고자 할 경우, 이동단말마다 운영체제가 상이하므로 프로그램 흐름의 제어, 인터럽트, IPC등 운영체제 특성을 반영한 별도의 구현이 필요하다. 이로 인하여 개발기간의 단축이 어려움은 물론 개발비용 증가, 개발인원의 투여, 시장 조기 진입의 어려움 등이 존재한다. 본 논문은 WAP을 다중 플렛폼에서 구현하기 위한 기저를 제공하는 추상 커널 계층(Abstract Kernel Layer)의 설계와 구현에 관한 것이다. 이는 REX, Palm, MS-DOS. MS-Window, UNIX 및 Linux를 포함한 각종 운영체제를 지원하는 커널 계층을 설계하여, 기기 종속적인 부분을 최소화되고 일관적인 인터페이스를 지원하여 개발 기간을 단축하고 소프트웨어의 유지보수를 용이하게 하는데 그 목적이 있다. 또한 추상 커널 계층은 mobile phone과 PDA에 탑재하여 그 실용성을 입증하였다.

• 한국정보처리학회논문지
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• 제4권11호
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• pp.2822-2831
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• 1997

ATM을 기반으로 하는 B-ISDN 망은 다양한 트래픽 특성과 서비스 요구사항을 가진 여러가지 종류의 서비스를 지원해야한다. ATM 계층에는 link 계층간의 흐름 제어나 에러 제어가 없다. 그러나 다양한 종류의 각종 서비스를 위해 각기 다른 다른 흐름／에러 제어 기법이 AAL 계층이나 상위 계층(예를 들어 OSI 7 계층의 4번 전송 계층)에서 수행될 수 있다. 전통적인 데이타망에서는 에러 제어 기법이 결합된 윈도우 흐름 제어 기법이 널리 사용되었다. 그러나 윈도우 흐름 제어 기법은 전파 전달 지연(Propagation delay)이 전송률(Transmission rate)에 비해 상대적으로 너무 크기 때문에 ATM 망에서 유용하지 않을 수 있다. 본 논문에서는 양단간(end-to-end) 자료 전송을 위한 매우 간단한 흐름제어 기법인 RCT (Rate Control for end-to-end Transport)를 제안한다. RCT는 평균 과부하(Overload) 기간의 분포가 특정 시간대에 편중되어 있을 때에 높은 성능을 보인다．

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.124-124
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• 2010

Currently, extreme ultraviolet lithography (EUVL) is being investigated for next generation lithography. EUVL is one of competitive lithographic technologies for sub-22nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance due to the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore, new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.127-128
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• 2008

The electrical characteristics of VARIOT (variable oxide thickness) with various $HfO_2$ thicknesses on thin $SiO_2$ or $Al_2O_3$ layer were investigated. Especially, the charge trapping characteristics of $HfO_2$ layer were intensively studied. The thin $HfO_2$ layer has small charge trapping characteristics while the thick $HfO_2$ layer has large memory window. Therefore, the $HfO_2$ layer is superior material and can be applied to charge storage as well as tunneling barrier of the non-volatile memory applications.

• 한국재료학회지
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• 제19권9호
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• pp.462-467
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• 2009

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

• Journal of Information Processing Systems
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• 제2권2호
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• pp.76-81
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• 2006

A PDA is used mainly for downloading data from a stationary server such as a desktop PC in an infrastructure network based on wireless LAN. Thus, the overall performance depends heavily on the performance of such downloading with PDA. Unfortunately, for a PDA the time taken to receive data from a PC is longer than the time taken to send it by 53%. Thus, we measured and analyzed all possible factors that could cause the receiving time of a PDA to be delayed with a test bed system. There are crucial factors: the TCP window size, file access time of a PDA, and the inter-packet delay that affects the receiving time of a PDA. The window size of a PDA during the downstream is reduced dramatically to 686 bytes from 32,581 bytes. In addition, because flash memory is embedded into a PDA, writing data into the flash memory takes twice as long as reading the data from it. To alleviate these, we propose three distinct remedies: First, in order to keep the window size at a sender constant, both the size of a socket send buffer for a desktop PC and the size of a socket receive buffer for a PDA should be increased. Second, to shorten its internal file access time, the size of an application buffer implemented in an application should be doubled. Finally, the inter-packet delay of a PDA and a desktop PC at the application layer should be adjusted asymmetrically to lower the traffic bottleneck between these heterogeneous terminals.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.31-38
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• 2002

0.35㎛-비아(via) 식각공정을 개선하기 위하여 C₂F/sub 6/가스의 식각특성을 분석하였다. 실험한 재료는 TEOS/SOG/TEOS 막을 올린 8인치 웨이퍼이며, 실험의 기법은 직교행열(Orthogonal array matrix) 실험 방식을 활용하였다. 산화막 식각에 이용된 장비는 transformer coupled plasma(TCP) source 방식이며 고밀도 플라즈마(HDP)장비이다. 실험의 결과는, 실험변수의 범위 내에서 C₂F/sub 6/는 0.8㎛/min-1.l㎛/min 범위의 식각속도를 보이며 균일도(Uniformity)는 ±6.9%미만으로 측정되었다. CD 변화(skew)는 식각 전과 후를 비교하여 10% 미만이었고 그 결과 비등방성(anisotropic) 식각의 특성이 우수하였다. C₂F/sub 6/를.20sccm 공급할 때 문제점이 발견되지 않았지만 14sccm을 공급하면 SOG 막의 내벽이 침식당하는 문제점이 있었다. 결과적으로 C₂F/sub 6/는 HDP TCP에서 빠른 식각비와 넓은 공정창(process window)을 가진 식각특성을 나타내었다.

• 대한금속재료학회지
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• 제48권3호
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.