• Journal of Advanced Marine Engineering and Technology
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• v.29 no.8
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• pp.915-922
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• 2005

This experimental study is conducted to investigate effects of a splitter plate, which is set on the back side of a square prism in the uniform flow. The Reynolds number is $1.44{\times}10^{4}$ based on the width of the square prism. The measurement of velocity vector and pressure distribution are carried out 4 cases of length in the range of 0.5L to 2.0L with 0.5L interval and 3 cases of Position at 0L, 0.25L, 0.5L, Flow visualization is also executed by smoke-wire method to understand the mechanism of vortex formation The results show the strong vortex shedding patterns and drags are decreased effectively, when the position of splitter plate is 0L. And the drag reduction rate is in inverse proportion to the splitter plate length

• Journal of Mechanical Science and Technology
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• v.18 no.4
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• pp.718-730
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• 2004

The solution for the natural convection in internally finned horizontal annuli is obtained by using a numerical simulation of time-dependent and two-dimensional governing equations. The fins existing in annuli influence the flow pattern, temperature distribution and heat transfer rate. The variations of the On configuration suppress or accelerate the free convective effects compared to those of the smooth tubes. The effects of fin configuration, number of fins and ratio of annulus gap width to the inner cylinder radius on the fluid flow and heat transfer in annuli are demonstrated by the distribution of the velocity vector, isotherms and streamlines. The governing equations are solved efficiently by using a parallel implementation. The technique is adopted for reduction of the computation cost. The parallelization is performed with the domain decomposition technique and message passing between sub-domains on the basis of the MPI library. The results from parallel computation reveal in consistency with those of the sequential program. Moreover, the speed-up ratio shows linearity with the number of processor.

• Proceedings of the KIEE Conference
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• 2007.10c
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• pp.135-137
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• 2007

In this paper, an advanced torque control scheme of SRM using DITC(Direct Instantaneous Torque Control) and PWM(pulse width modulation) is presented. Different from conventional DITC method, proposed method uses one or two switching modes at every sampling time, instead of only one switching mode. The duty ratio of the phase switch is regulated according to the torque error and simple control rules of DITC. Moreover the sampling time of control can be extended, which allows implementation on low cost microcontrollers. The proposed control method is verified by the simulations and experimental results.

• Steel and Composite Structures
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• v.15 no.2
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• pp.131-150
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• 2013

This paper presents the experimental results of axially loaded stub columns of slender steel hollow square section (SHS) strengthened with carbon fiber reinforced polymers (CFRP) sheets. 9 specimens were fabricated and the main parameters were: width-thickness ratio (b/t), the number of CFRP ply, and the CFRP sheet orientation. From the tests, it was observed that two sides would typically buckle outward and the other two sides would buckle inward. A maximum increase of 33% was achieved in axial-load capacity when 3 layers of CFRP were used to wrap HSS columns of b/t = 100 transversely. Also, stiffness and ductility index (DI) were compared between un-retrofitted specimens and retrofitted specimens. Finally, it was shown that the application of CFRP to slender sections delays local buckling and subsequently results in significant increases in elastic buckling stress. In the last section, a prediction formula of the ultimate strength developed using the experimental results is presented.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.7-9
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• 2014

본 논문에서는 하드웨어 기반의 Sample Adaptive Offset (SAO) 부호화기에서 전체 면적 중 상당히 큰 비중을 차지하는 통계값 테이블의 면적을 개선하는 방법을 제안한다. 파이프라인으로 동작하는 통계 계산과 최적 모드 결정 모듈의 통계값 테이블 접근 분석을 통하여 Luma 테이블을 재사용함으로써 Cr 테이블을 제거할 수 있다. 또한 테이블의 bit width 를 가능한 값의 최대 범위가 아닌, 충분히 큰 범위로 제한함으로써 면적을 감소시킬 수 있다. 제안한 방법을 적용했을 때 합성을 통해 예측된 면적이 46% 가량 감소하는 것을 확인하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.839-841
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• 2004

This paper presents a SPMSM servo motor drive system using high performance TMS320 F281T DSP for the industrial application. This high performance DSP contains some special peripheral circuits such as PWM (Pulse Width Modulation) waveform generation circuit, Quadrature Encoder Pulse (QEP) generation circuit and Analog to Digital Converter (ADC) circuit. In this paper, a servo drive control system is constructed using high performance DPS for the overall system cost reduction and the size minimization.

• Journal of Power Electronics
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• v.12 no.4
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• pp.643-653
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• 2012

An interleaved DC/DC converter with series-connected transformers is presented to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two half-bridge converter cells connected in series to reduce the voltage stress of the switches at one-half of the input voltage. The output sides of the two converter cells with interleaved pulse-width modulation are connected in parallel to reduce the ripple current at the output capacitor and to achieve load current sharing. Therefore, the size of the output chokes and the capacitor can be reduced. The output capacitances of the MOSFETs and the resonant inductances are resonant at the transition instant to achieve ZVS turn-on. In addition, the switching losses on the power switches are reduced. Finally, experiments on a laboratory prototype (24V/40A) are provided to demonstrate the performance of the proposed converter.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.847-850
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• 1998

One of the most difficult problem of designing VLSI is a mixed-circuit design, that is to design circuit containing both analog parts and digital parts. Digital to analog converter and analog to digital converter is a typical case. Especially it can be a serious problem when mixed circuit are put into a large digital circuit like microcontroller. However nowadays this problem is settled by separating analog circuit parts outside the IC. This technique is based on converting a digital signal into a pulse sequence. Then an analog signal is obtained by averaging this pulse sequence at the external low-pass filter. An anlog to digital converter is designed using a stochastic logic instead of a traditional PWM (pulse-width modulation) signal and ins implemente dusing FPGa. Stochastic pulse sequence can be made as a simple circuits and moreover can be mathematically processed by simple circuits -AND gates. The spectral property of stochastic pulse sequence method is better than that of PWM method. So it make easy to design a external low-pass filter. This technique has important advantages, especially the reduction of the ADC cost.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.