• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.57-61
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• 1985

The e(lect of capacitance error on the A/D conversion accuracy in the A/D converter using binary-weighted capacitor array was scruntized. Besides the Monte-Carlo method considering the inter-capacitance ratios as random variables, " correlation approach" con-sidering the correlation coefficient between capacitances is proposed in this paper. Bt was observed by the measurement of capacitances of monolithic MO5 capacitors that the correla-tion coefficient between capacitors decreases as the capacitor size incrrases. It was also verified that the parallel connection of unit capacitors and the common centroid layout scheme signi(icantly increase the inter-capacitance correlation coefficients.

• Journal of Power Electronics
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• v.19 no.1
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• pp.89-98
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• 2019

This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.863-866
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• 1998

In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.613-618
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• 2004

CCS was developed and applied to rotating machines because of accurately measuring the spindle error motion without significant efforts. However, researches on the CCS have been focused on ideal cases where circumferential gaps were ignored. This paper presents the effects of circumferential gaps and proposes an optimal CCS considering the circumferential gaps. First, electrostatic analysis of the CCS that includes the circumferential gaps is performed using the FEM, and an additional capacitance due to the circumferential gap can be approximated as an equivalent extended sensor length. Second, a mathematical model of the CCS considering the circumferential gaps is derived, and the optimal CCS is determined through minimization of the weighted error amplification factor. Finally, two CCSs, both considering and ignoring the circumferential gaps, are built, and the effectiveness of the optimal design is verified through simulation and experiment.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.52-59
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• 1991

An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.10-16
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning scheme for PHS applications. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$ and the phase noise is -121dBc/Hz at 600kHz offset. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1304-1310
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• 2021

Two-phase flow, especially gas-liquid two-phase flow, has a wide application in industrial field. The diagnosis of two-phase flow parameters, which directly determine the flow and heat transfer characteristics, plays an important role in providing the design reference and ensuring the security of online operation of two-phase flow system. Computer tomography (CT) is a good way to diagnose such parameters with imaging method. This paper has proposed a novel image reconstruction method for thermal neutron CT of two-phase flow with improved simulated annealing (ISA) algorithm, which makes full use of the prior information of two-phase flow and the advantage of stochastic searching algorithm. The reconstruction results demonstrate that its reconstruction accuracy is much higher than that of the reconstruction algorithm based on weighted total difference minimization with soft-threshold filtering (WTDM-STF). The proposed method can also be applied to other types of two-phase flow CT modalities (such as X(𝛄)-ray, capacitance, resistance and ultrasound).