• Journal of the Semiconductor & Display Technology
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• v.2 no.2
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• pp.9-15
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• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.621-622
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• 2012

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.12
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• pp.1072-1080
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• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.4
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• pp.481-488
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• 1999

A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

• Transactions of Materials Processing
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• v.14 no.5 s.77
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• pp.477-481
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• 2005

Wafer scale micro mirror array with high surface quality for small form factor (SFF) optical pick-up was fabricated by micro UV-molding. To replicate micro mirror array for SFF optical pick-up, a high- precision mold was fabricated using micro-machining technology. Wafer scale micro mirror array was UV-molded using the mold and then the process was optimized experimentally. The surface flatness and roughness of UV-molded micro mirror array were measured by white light scanning interferomety system and analyzed the transcribing characteristics. Finally, the measured flatness of UV-molded micro mirror away for SFF optical pick-up, which was fabricated in the optimum processing condition, was less than 70nm.

• Laser Solutions
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• v.5 no.2
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• pp.9-15
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• 2002

Basic principles and unique characteristics of laser-induced shock cleaning have been described compared to a conventional laser cleaning method and the removal of small tungsten particles from silicon wafer surfaces was attempted using both methods. It was found that the conventional laser cleaning was not feasible to remove the tungsten particles whereas a successful removal of the particles was carried out by the laser-induced shock waves. From the quantitative analysis using a surface scanner, the average removal efficiency of the particles was more than 98% where smaller particles were slightly more difficult to remove probably due to the increased adhesion force with a decrease of the particle size. It was also seen that the gap distance between the laser focus and the wafer surface is an important processing parameter since the removal efficiency is strongly dependent on the gap distance.

• Journal of Korea Multimedia Society
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• v.13 no.3
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• pp.400-409
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• 2010

This paper presents a position error recognition system when the wafer is mounted in cleaning equipment among the wafer manufacturing processes. The proposed system is to enhance the performance in cost and reliability by preventing the wafer cleaning system from damaging by alerting it when it is put in correct position. The key algorithms are the calibration method between image acquired from camera and physical wafer, a infrared lighting and the design of the filter, and the extraction of wafer boundary and the position error recognition resulting from generation of circle based on least square method. The system is to install in-line process using high reliable and high accurate position recognition. The experimental results show that the performance is good in detecting errors within tolerance.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of Korea Foundry Society
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• v.33 no.4
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• pp.157-161
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• 2013

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was ${\geq}$ 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.