• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1068-1071
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• 2001

Recently, the minimum line width shows a tendancy to decrease and the multi-level to increase in semiconductor. Therefore, a planarization technique is needed, which chemical polishing(CMP) is considered as one of the most important process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as microscratches, abrasive contaminations, and non-uniformity of polished wafer edges. Spin Etching can improve the defects of CMP. It uses abrasive-free chemical solution instead of slurry. Wafer rotates and chemical solution is simultaneously dispensed on a whole surface of the wafer. Thereby chemical reaction is occurred on the surface of wafer, material is removed. On this study, TEOS film is removed by CMP and Spin Etching, the results are estimated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU).

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.9
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• pp.2315-2328
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• 1993

The turbulence effect of particle deposition on a horizontal free-standing wafer in a vertical flow has been studied numerically by using the low-Reynolds-number k-.epsilon. turbulence model. For both the upper and lower surfaces of the wafer, predictions are made of the averaged particle deposition velocity and its radial distribution. Thus, it is now possible to obtain local information about the particle deposition on a free-standing wafer. The present result indicates that the particle deposition velocity on the lower surface of wafer is comparable to that on the upper one in the diffusion controlled deposition region in which the particle sizes are smaller than $0.1{\mu}m$. And it is found in this region that, compared to the laminar flow case, the averaged deposition velocity under the turbulent flow is about two times higher, and also that the local deposition velocity at the center of wafer is high equivalent to that the wafer edge.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.50.1-50.1
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• 2010

결정질 실리콘 태양전지의 원가에서 Wafer는 60~70%의 매우 높은 비중을 차지하고 있다. 많은 연구들이 원가 절감을 위하여 Wafer의 두께를 감소시키는 것에 집중하고 있다. 그러나 Wafer 두께의 감소는 태양전지의 효율 감소와 공정 진행 중에 파손율이 상승하는 등의 문제가 발생한다. 이에 본 논문에서는 결정질 태양전지 구조 중에서 24.7% 이상의 최고 변환 효율을 갖는 PERL(Passivated Emitter, Rear Locally diffuse) 구조를 대상으로 wafer 두께 감소에 따른 변환 효율 감소의 원인과 해결 방안을 제시하고자 한다. Simulation으로 확인한 결과 370 um 두께의 wafer에서 24.2 %의 효율은 50 um 두께의 wafer에서는 20.8 %로 감소함을 확인할 수 있었다. 얇아진 wafer에서 감소한 효율을 개선하기 위하여 후면 recombination velocity, 후면 fixed charge density, 후면 산화막 두께 등을 다양화하여, 각각의 경우에 대한 cell의 효율 변화를 살펴보았다. 그 결과 후면 recombination velocity, 후면 fixed charge density, 후면 산화막 두께를 최적화 하여, 각각 2.8 %p, 1.5 %p, 2.8 %p의 효율 개선 효과를 얻었다. 위 세 가지 효과를 동시에 적용하면 50 um wafer에서 370 um wafer 효율의 결과와 근접한 24.2 %의 효율을 얻을 수 있었다. 향후에는 위의 결과를 바탕으로 실제 실험을 통하여 확인할 계획이다.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• Tribology and Lubricants
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• v.35 no.6
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• pp.323-329
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• 2019

Sapphire is currently used as a substrate material for blue light-emitting diodes (LEDs). The market for sapphire substrates has expanded rapidly as the use of LEDs has extended into various industries. However, sapphire is classified as one of the most difficult materials to machine due to its hardness and brittleness. Recently, a lap-grinding process has been developed to combine the lapping and diamond mechanical polishing (DMP) steps in a single process. This paper studies, the effect of wafer surface roughness on the chemical mechanical polishing (CMP) process by pressure and abrasive concentration in the lap-grinding process of a sapphire wafer. In this experiment, the surface roughness of a sapphire wafer is measured after lap-grinding by varying the pressure and abrasive concentration of the slurry. CMP is carried out under pressure conditions of 4.27 psi, a plate rotation speed of 103 rpm, head rotation speed of 97 rpm, and slurry flow rate of 170 ml/min. The abrasive concentration of the CMP slurry was 20wt, implying that the higher the surface roughness after lapgrinding, the higher the material removal rate (MRR) in the CMP. This is likely due to the real contact area and actual contact pressure between the rough wafer and polishing pad during the CMP. In addition, wafers with low surface roughness after lap-grinding show lower surface roughness values in CMP processes than wafers with high surface roughness values; therefore, further research is needed to obtain sufficient surface roughness before performing CMP processes.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.4 s.235
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• pp.632-638
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• 2005

The surface lapping process on sapphire wafer was carried out for the epitaxial process of thin film growth of GaN semiconducting material. The planarization of the wafers was investigated by the introduction of the dummy wafers. The diamond lapping process causes the surface deformation of dislocation and micro-cracks. The material deformation due to the mechanical stress was analyzed by the X-ray diffraction and the Vickers indentation. The fracture toughness was increased with the increased annealing temperature indicating the recrystallization at the surface of the sapphire wafer The sudden increase at the temperature of $1200^{\circ}C$ was correlated with the surface phase transition of sapphire from a $-A1_{2}O_{3}\;to\;{\beta}-A1_{2}O_{3}$.

• Journal of ILASS-Korea
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• v.12 no.4
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• pp.185-190
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• 2007

There is a growing interest to develop a new cleaning technology to overcome the disadvantages of wet cleaning technologies such as environmental pollution and the cleaning difficulty of contaminants on integrated circuits. Laser cleaning is a potential technology to remove various pollutants on a wafer surface. However, there is no fundamental data about cleaning efficiencies and cleaning mechanisms of contaminants on a wafer surface using a laser cleaning technology. Therefore, the cleaning characteristics of a wafer surface using an excimer laser were investigated in this study. Fingerprint consisting of inorganic and organic materials was chosen as a representative of pollutants and the effectiveness of a laser irradiation on a wafer cleaning has been investigated qualitatively and quantitatively. The results have shown that cleaning degree is proportional to the laser irradiation time and repetition rate, and quantitative analysis conducted by an image processing method also have shown the same trend. Furthermore, the cleaning efficiency of a wafer contaminated by fingerprint strongly depended on a photothermal cleaning mechanism and the species were removed in order of hydrophilic and hydrophobic contaminants by laser irradiation.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.42-45
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• 2002

General wheel mark in mono-crystalline silicon wafer finding is able to be expected because it depends on radius ratio and angular velocity ratio of wafer and wheel. The pattern is predominantly determined by the contour of abrasive grits resulting from a relative motion. Although such a wheel mark is made uniform pattern if the process parameters are fixed, sub-surface defect is expected to be distributed non-uniformly because of characteristic of mono-crystalline silicon wafer that has diamond cubic crystal. Consequently it is considered that this phenomenon affects the following process. This paper focused on kinematic analysis of wafer grinding process and simulation program was developed to verify the effect of process variables on wheel mark. And finally, we were able to predict sub-surface defect distribution that considered characteristic of mono-crystalline silicon wafer

• Journal of the Optical Society of Korea
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• v.11 no.4
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• pp.173-176
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• 2007

We present a very simple and efficient bare-wafer inspection method using a knife-edge test. The wafer front surface and inner structures are inspected simultaneously. The wafer front surface is inspected visually using a knife-edge test while the inner structure is simultaneously inspected by a camera in the infrared region with a single white-light source. This paper presents a laboratory implementation of the test method with some experimental results.