• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 춘계학술대회 논문집
• /
• pp.434-437
• /
• 2005

Chemical Mechanical Polishing (CMP) has become an essential step in the overall semiconductor wafer fabrication technology. In general, CMP is a surface planarization method in which a silicon wafer is rotated against a polishing pad in the presence of slurry under pressure. The polishing pad, generally a polyurethane-based material, consists of polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. It has been found that the material removal rate of any polishing pad decreases due to the so-called 'pad glazing' after several wafer lots have been processed. Therefore, the pad restoration and conditioning has become essential in CMP processes to keep the urethane polishing pad at the proper friction coefficient and to allow effective slurry transport to the wafer surface. Diamond pad conditioner employs a single layer of brazed bonded diamond crystals. Due to the corrosive nature of the polishing slurry required in low pH metal CMP such as copper, it is essential to minimize the possibility of chemical interaction between very low pH slurry (pH <2) and the bond alloy. In this paper, we report an exceptional protective coated conditioner for in-situ pad conditioning in low pH Cu CMP process. The protective Cr-coated conditioner has been tested in slurry with pH levels as low as 1.5 without bond degradation.

• Current Photovoltaic Research
• /
• 제5권2호
• /
• pp.59-62
• /
• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.

• 한국공작기계학회논문집
• /
• 제16권5호
• /
• pp.90-95
• /
• 2007

Single side final polishing is a very important role to stabilize a wafer finally before the device process on the wafer is executed. In this study, the machining variables, such as pressure, machining time, and the velocity of pad table were adopted. These parameters have the major influence on the characteristics of wafer polishing. We investigated the surface roughness changing these variables to find the optimal polishing condition. Pad, slurry, slurry quantity, and oscillation distance were set to the fixed variables. In order to reduce defects and find a stable machining condition, a hall sensor was used on the polishing process. AE sensor was attached to the polishing machine to verify optimal condition. Applying data analysis of the sensor signal, experiments were performed. We can get better surface roughness from loading the quasi static force and improving wafer-holding method.

• Journal of Welding and Joining
• /
• 제19권3호
• /
• pp.305-310
• /
• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.

• 대한기계학회논문집B
• /
• 제21권10호
• /
• pp.1284-1293
• /
• 1997

The electrostatic effect on particle deposition onto a heated, Horizontal free-standing wafer surface was investigated numerically. The deposition mechanisms considered were convection, Brownian and turbulent diffusion, sedimentation, thermophoresis and electrostatic force. The electric charge on particle needed to calculate the electrostatic migration velocity induced by the local electric field was assumed to be the Boltzmann equilibrium charge. The electrostatic forces acted upon the particle included the Coulombic, image, dielectrophoretic and dipole-dipole forces based on the assumption that the particle and wafer surface are conducting. The electric potential distribution needed to calculate the local electric field around the wafer was calculated from the Laplace equation. The averaged and local deposition velocities were obtained for a temperature difference of 0-10 K and an applied voltage of 0-1000 v.The numerical results were then compared with those of the present suggested approximate model and the available experimental data. The comparison showed relatively good agreement between them.

• 한국입자에어로졸학회지
• /
• 제14권2호
• /
• pp.41-47
• /
• 2018

Numerical analysis was conducted to characterize particle deposition onto a heated horizontal semiconductor wafer in vacuum environment. In order to calculate the properties of gas surrounding the wafer, the gas was assumed to obey the ideal gas law. Particle transport mechanisms considered in the present study were convection, Brownian diffusion, gravitational settling and thermophoresis. Averaged particle deposition velocities on the upper surface of the wafer were calculated with respect to particle size, based on the numerical results from the particle concentration equation in the Eulerian frame of reference. The deposition velocities were obtained for system pressures of 1000 Pa~1 atm, wafer heating of 0~5 K and particle sizes of $2{\sim}10^4nm$. The present numerical results showed good agreement with the available experimental ones.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
• /
• pp.38-39
• /
• 2005

We have investigated the effect of the pad surface characteristics such as roughness, groove density and wear of pad on within wafer non-uniformity(WIWNU) in chemical mechanical polishing(CMP). We found that WIWNU increases as pad surface roughness($R_{pk}$; Reduced peak height) increases in an early stage of polishing. But after polishing time goes to a certain extent, WIWNU decreases as uniformity of pad surface roughness. Also, groove of pad has effect on relative pad stiffness although original mechanical properties of pad are unchanged by grooving. WIWNU decreases as relative pad stiffness decreases. In addition, conditioning process causes non-uniform wear of pad during in CMP. The profile of pad wear has a significant effect on WIWNU.

• 한국정밀공학회지
• /
• 제19권7호
• /
• pp.51-58
• /
• 2002

In this paper, the characteristics of silicon wafer surface which is textured by KOH anisotropic etching method and mechanical polishing are investigated from the viewpoint of stiction and friction. It was found that the characteristics of stiction and friction of each textured surface are dependent on the contact area characterized by surface parameters such as bearing length ratio and peak count. To find the mechanism of the variation of stiction and friction in textured surface, OTS SAM coated wafer was used. In this case, the variation of stiction and friction was diminished, Therefore, it is concluded that the reason of variation of stiction and friction on textured surface is mainly caused by capillary which in turn is affected by the surface topography

• 한국결정성장학회지
• /
• 제11권3호
• /
• pp.89-95
• /
• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.

• 한국입자에어로졸학회지
• /
• 제5권1호
• /
• pp.17-27
• /
• 2009

Particle deposition on a semiconductor wafer larger than 100 mm was studied experimentally and numerically. Particularly the electrostatic effect on particle deposition velocity was investigated. The experimental apparatus consisted of a particle generation system, a particle deposition chamber and a wafer surface scanner. Experimental data of particle deposition velocity were obtained for a semiconductor wafer of 200 mm diameter with the applied voltage of 5,000 V and PSL particles of the sizes between 83 and 495 nm. The experimental data of particle deposition velocity were compared with the present numerical results and the existing experimental data for a 100 mm wafer by Ye et al. (1991) and Opiolka et al. (1994). The present numerical method took into consideration the particle transport mechanisms of convection, Brownian diffusion, gravitational settling and electrostatic attraction in an Eulerian frame of reference. Based on the comparison of the present experimental and numerical results with the existing experimental results the present experimental method for a 200 mm semiconductor wafer was found to be able to present reasonable data.