• 한국정밀공학회지
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• 제29권3호
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• pp.289-294
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• 2012

There are several indicators to represent characteristics of chemical mechanical planarization (CMP) such as material removal rate (MRR), surface quality and removal uniformity on a wafer surface. Especially, the removal uniformity on the wafer edge is one of the most important issues since it gives a significant impact on the yield of chip production on a wafer. Non-uniform removal rate at the wafer edge (edge effect) is mainly induced by a non-uniform pressure from nonuniform pad curvature during CMP process, resulting in edge exclusion which means the region that cannot be made to a chip. For this reason, authors tried to minimize the edge exclusion by using an edge profile control (EPC) ring. The EPC ring is equipped on the polishing head with the wafer to protect a wafer from the edge effect. Experimental results showed that the EPC ring could dramatically minimize the edge exclusion of the wafer. This study shows a possibility to improve the yield of chip production without special design changes of the CMP equipment.

• ETRI Journal
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• 제36권4호
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• pp.617-624
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• 2014

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as three-dimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.277-277
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• 2011

디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.118-118
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• 2008

The oxide CMP has been applied to interlayer dielectric(ILD) and shallow trench isolation (STI) in chip fabrication. Recently the slurry used in oxide CMP being changed from silica slurry to ceria (cerium dioxide) slurry particularly in STI CMP, because the material selectivity of ceria slurry is better than material selectivity of silica slurry. Moreover, the ceria slurry has good a planarization efficiency, compared with silica slurry. However ceria abrasives make a material removal rate too high at the region of wafer center. Then we focuses on why profile of material removal rate is convex. The material removal rate sharply increased to 3216 $\AA$/min by $4^{th}$ run without conditioning. After $4^{th}$ run, material removal rate converged. Furthermore, profile became more convex during 12 run. And average material removal rate decreased when conditioning process is added to end of CMP process. This is due to polishing mechanism of ceria. Then the ceria abrasive remains at the pad, in particular remains more at wafer center contacted region of pad. The field emission scanning electron microscopy (FE-SEM) images showed that the pad sample in the wafer center region has a more ceria abrasive than in wafer outer region. The energy dispersive X-ray spectrometer (EDX) verified the result that ceria abrasive is deposited and more at the region of wafer center. Therefore, this result may be expected as ceria abrasives on pad surface causing the convex profile of material removal rate.

• 대한전자공학회논문지
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• 제25권6호
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.363-364
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.755-756
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• 2007

• 반도체디스플레이기술학회지
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• 제5권2호
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• pp.41-46
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• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• 한국정밀공학회지
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• 제34권2호
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• pp.107-114
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• 2017

In this investigation, we describe a metrological technique for surface and thickness profiles of a silicon (Si) wafer by using a 6 degree of freedom (DOF) stitching method. Low coherence scanning interferometry employing near infrared light, partially transparent to a Si wafer, is adopted to simultaneously measure the surface and thickness profiles of the wafer. For the large field of view, a stitching method of the sub-aperture measurement is added to the measurement system; also, 6 DOF parameters, including the lateral positioning errors and the rotational error, are considered. In the experiment, surface profiles of a double-sided polished wafer with a 100 mm diameter were measured with the sub-aperture of an 18 mm diameter at $10\times10$ locations and the surface profiles of both sides were stitched with the sub-aperture maps. As a result, the nominal thickness of the wafer was $483.2{\mu}m$ and the calculated PV values of both surfaces were $16.57{\mu}m$ and $17.12{\mu}m$, respectively.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.316-316
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• 2012

본 연구에서는 Si wafer에 마스크 공정 및 Slit-etching 공정을 적용하여 25 um 피치의 probe unit을 개발하기 위해 Deep Si Etching 장비를 이용하여 식각공정 조건에 따른 특성을 평가하였다. 25 um pitch는 etch 폭의 크기에 따라 3종류로 설계하였으며, 식각공정은 2수준, 4인자 실험계획법에 의해 8회 실험을 수행하였다. 실험계획법에 의해 미니탭을 활용하여 최적조건을 구한 결과 12.5 um etch 폭에서는 가스유량은 200 sccm, 에칭시간 7 sec, 코일 파워 1500W, 에칭 압력은 43.7 mtorr의 조건이 etch 형태 및 profile angle이 목표치에 근접한 결과를 얻었다. 또한 probe pitch를 30~60 um까지 증가시켰을 경우 Etch depth는 증가하였으며, 식각율 또한 증가한 현상을 보였다. 재현성 실험을 위해 위의 최적조건을 이용하여 2회 반복하여 실험한 경우 모든 시편이 목표치에 도달하였다. 이는 미세피치화 되는 프로브 유닛의 기초데이터로 활용될 수 있다.