• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2012년도 추계총회 및 학술대회 논문집
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• pp.71-71
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• 2012

Memory 반도체 Test공정에서 사용되는 Probe Card의 Probing Area가 넓어지면서 종래에 사용되던 Cantilever제품의 사용이 불가능하게 되고, MEMS공정을 사용한 새로운 형태의 Advanced제품이 시장에 출현을 하였다. MEMS형의 제품은 다수의 Micro Spring을 MLC(Multi Layer Ceramic)위에 MEMS 공정을 사용하여 생성하는 방식으로서 MLC는 좁은 지역에 다수의 Pin을 생성 할 수 있는 공간을 만들어 주며, 또 다른 이유는 전기적 특성인 임피던스를 맞추고 다수의 Pin의 압력에 의하여 생기는 하중을 Ceramic기판으로 지탱하기 위한 목적도 있다. 이에 MLC와 같은 전기적 특성을 임피던스를 맞춘 RF-CPCB를 사용하여 작은 면적에 다수의 Pin접합이 가능한 방법을 마련한 후, 이 RF-PCB를 부착하여 Pin의 하중을 받는 Wafer와 유사한 열팽창을 갖는 Substrate를 사용하여 MLC를 대체하여 다양한 온도 조건에서 사용이 가능하며, 복잡하고 공정비가 많이 드는 MEMS 공정에 의한 일괄 Micro Spring 생성 공정을 전주 도금 또는 2D방식의 도금 Pin으로 대체하였으며, Probe Card의 중요한 물리적 특성인 Pin들의 정렬도를 마련하기 위해 Photo Process를 사용한 Wafer로 만든 Wafer Pin Array Frame을 사용하여 2D 제작 Pin을 일괄 또는 부분 접합이 가능한 방법으로 Probe Array Head를 제작하여 이들을 부착하여 Probe Array Head를 이전의 MEMS공정 방법에 비해 쉽고 빠르게 만들어 probe Card를 제작 할 수 있게 되었다.

• 전기학회논문지
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• 제60권7호
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• pp.1434-1437
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• 2011

Precision measurement of silicon wafer resistivity has been using single-configuration Four-Point Probe(FPP) method. This FPP method have to applying sample size, shape and thickness correction factor for a probe pin spacing to precision measurement of silicon wafer. The deference for resistivity measurement values applied correction factor and not applied correction factor was about 1.0 % deviation. The sample size, shape and thickness correction factor for a probe pin spacing have an effects on precision measurement for resistivity of silicon wafer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.1265-1266
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• 2013

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.811-812
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• 2012

• 한국전기전자재료학회논문지
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• 제19권9호
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• 한국정밀공학회지
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• 제17권1호
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• pp.129-137
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• 2000

In this paper, a new method of noncontact measurement has been developed for a 3 dimensional topography in semiconductor wafer, implementing a new optical probe based on the precision defocus measurement. The developed technique consists of the new optical probe, precision stages, and the measurement/control system. The basic principle of the technique is to use the reflected slit beam from the specimen surface, and to measure the deviation of the specimen surface. The defocusing distance can be measured by the reflected slit beam, where the defocused image is measured by the proposed optical probe, giving very high resolution. The distance measuring formula has been proposed for the developed probe, using the laws of geometric optics. The precision calibration technique has been applied, giving about 10 nanometer resolution and 72 nanometer of four sigma uncertainty. In order to quantitize the micro pattern in the specimen surface, some efficient analysis algorithms have been developed to analyse the 3D topography pattern and some parameters of the surface. The developed system has been successfully applied to measure the wafer surface, demonstrating the line scanning feature and excellent 3 dimensional measurement capability.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.277-277
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• 2011

디스플레이의 기술발전에 의해 대면적 고해상도의 LCD가 제작되어 왔다. 이에 따라 LCD 점등검사를 위한 Probe Unit의 기술 또한 급속도로 발전하고 있다. 고해상도에 따라 TFT LCD pad가 미세피치화 되어가고 있으며, panel의 검사를 위한 Probe 또한 30 um 이하의 초미세피치를 요구하고 있다. 따라서, 초미세 pitch의 LCD panel의 점등검사를 위한 Probe Unit의 개발이 시급하가. 본 연구에서는 30 um 이하의 미세피치의 Probe block을 위한 Slit wafer의 식각 공정 조건을 연구하였다. Si 공정에서 식각율과 식각깊이에 따른 profile angle의 목표를 설정하고, 식각조건에 따라 이 두 값의 변화를 관측하였다. 식각실험으로 Si DRIE 장비를 이용하여, chamber 압력, cycle time, gas flow, Oxygen의 조건에 따라 각각의 단면 및 표면을 SEM 관측을 통해 최적의 식각 조건을 찾고자 하였다. 식각율은 5um/min 이상, profile angle은 $90{\pm}1^{\circ}$의 값을 목표로 하였다. 이 때 최적의 식각조건은 Etching : SF6 400 sccm, 10.4 sec, passivation : C4F8 400 sccm, 4 sec의 조건이었으며, 식각공정의 Coil power는 2,600 W이었다. 이러한 조건의 공정으로 6 inch Si wafer에 공정한 결과 균일한 식각율 및 profile angle 값을 보였으며, oxygen gas를 미량 유입함으로써 식각율이 균일해짐을 알 수 있었다. 결론적으로 최적의 Slit wafer 식각 조건을 확립함으로써 Probe Unit을 위한 Pin 삽입공정 또한 수율 향상이 기대된다.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.22-25
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• 2005

In this research, a wafar-level transfer method of cantilever array on a conventional CMOS circuit has been developed for high density probe-based data storage. The transferred cantilevers were silicon nitride ($Si_3N_4$) cantilevers integrated with poly silicon heaters and piezoelectric sensors, called thermo-piezoelectric $Si_3N_4$ cantilevers. In this process, we did not use a SOI wafer but a conventional p-type wafer for the fabrication of the thermo-piezoelectric $Si_3N_4$ cantilever arrays. Furthermore, we have developed a very simple transfer process, requiring only one step of cantilever transfer process for the integration of the CMOS wafer and cantilevers. Using this process, we have fabricated a single thermo-piezoelectric $Si_3N_4$ cantilever, and recorded 65nm data bits on a PMMA film and confirmed a charge signal at 5nm of cantilever deflection. And we have successfully applied this method to transfer 34 by 34 thermo-piezoelectric $Si_3N_4$ cantilever arrays on a CMOS wafer. We obtained reading signals from one of the cantilevers.

• 한국생산제조학회지
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• 제20권4호
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• pp.395-400
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• 2011

Scanning Probe Lithography is a method to localized oxidation on single crystal silicon wafer surface. This study demonstrates nanometer scale non contact lithography process on (100) silicon (p-type) wafer surface using AFM(Atomic force microscope) apparatuses and pulse controlling methods. AFM-based experimental apparatuses are connected the DC pulse generator that supplies ultra short pulses between conductive tip and single crystal silicon wafer surface maintaining constant humidity during processes. Then ultra short pulse durations are controlled according to various experimental conditions. Non contact lithography of using ultra short pulse induces electrochemical reaction between micro-scale tip and silicon wafer surface. Various growths of oxides can be created by ultra short pulse non contact lithography modification according to various pulse durations and applied constant humidity environment.