• Journal of Korean Institute of Industrial Engineers
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• v.36 no.1
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• pp.42-51
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• 2010

The semiconductor industry is highly capital and technology intensive. Technology advancement on circuit design and process improvement requires chip makers continuously to invest a new fabrication facility that costs more than 3 billion US dollars. Especially major semiconductor companies recently started to discuss 450mm fabrication substituting existing 300mm fabrication of which facilities were initiated to build in 1998. If the plan is consolidated, the yield of 450mm facility would be more than doubled compared to existing 300mm facility. In steps of this important investment, facility layout has been acknowledged as one of the most important factors to be competitive in the market. This research proposes a new concept of semiconductor facility layout using hexagonal floor plan and its compatible material flow pattern. The main objective of this proposal is to improve the productivity of the unified layout that has been popularly used to build existing facilities. In this research, practical characteristics of the semiconductor fabrication are taken into account to develop a new layout alternative based on the analysis of Chung and Tanchoco (2009). The performance of the proposed layout alternative is analyzed using computer simulation and the results show that the new layout alternative outperforms the existing layout alternative, unified layout. However, a few questions on space efficiency to the new alternative were raised in communication with industry practitioners. These questions are left for a future study.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.