• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.107-113
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• 2024

Scheduling of semiconductor test facilities has been crucial since effective scheduling contributes to the profits of semiconductor enterprises and enhances the quality of semiconductor products. This study aims to solve the scheduling problems for the wafer burn-in test facilities of the semiconductor back-end process by utilizing simulation and deep reinforcement learning-based methods. To solve the scheduling problem considered in this study. we propose novel state, action, and reward designs based on the Markov decision process. Furthermore, a neural network is trained by employing the recent RL-based method, named proximal policy optimization. Experimental results showed that the proposed method outperformed traditional heuristic-based scheduling techniques, achieving a higher due date compliance rate of jobs in terms of total job completion time.

• Journal of Satellite, Information and Communications
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• v.1 no.2
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• pp.56-62
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• 2006

This paper describes the MMIC product qualification of the Ka band satellite transponder for the COMS(Communication, Ocean and Meteorological Satellite). Ka-band active equipment for the COMS communications transponder are being developed by using 12 kinds of MMICs which include low noise amplifiers, medium power amplifiers, frequency mixers, frequency multipliers, RF switch, and HEMT attenuator MMIC, Those MMICs had been fabricated at the MMIC production foundry of northrop Grumman Space Technology (Velocium) which is qualified for space application, and experienced in various space programs during past decades. For the MMIC product qualification, Visual inspection and SEM inspection had been performed, and burn-in test for 240 hours and accelerated life-test for 1000 hours had been done on test fixtures of individual MMIC products at $125^{\circ}C$. Additionally, infrared temperature scanning and finite element simulation were performed to analyze and confirm the channel temperature of semiconductor devices on several representatives of those MMIC products that os one of the most important factors in performance degradation and life reduction.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.