• Proceedings of the Korean Nuclear Society Conference
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• 2005.05a
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• pp.1265-1266
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• 2005

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.304-308
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• 2009

This paper presents the deadline driven CPU-Power management scheme for the Real-Time Embedded OS: named TMO-eCos. It used the scheduling scenarios generated by a task serialization technique for hard real- time TMO system. The serializer does a off-line analysis at design time with period, deadline and WCET of periodic tasks. Finally, TMO-eCos kernel controls the CPU speed to save the power consumption under the condition that periodic tasks do not violate deadlines. As a result, the system shows a reasonable amount of power saving. This paper presents all of these processes and test results.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.505-507
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• 2005

In this paper, a timing analysis is performed for the CAN-based simulator system for a fuel cell hybrid electric vehicles. The CAN protocol is recently being used for conventional vehicles, however, the network-induced delay can make the in-vehicle network system unstable. This problem may be occurred in the future vehicles because more ECUs are being required than recent vehicles. In order to develop a stable network-based control system, timing analysis is required at the design process. Throughout this analysis, timing parameters that affect transmission delay are examined and an effective method of predicting a sampling time for a stable communication via CAN protocol. In order to show the validityof suggested timing analysis. some experiments are performed using DSPs with CAN module.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.467-478
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• 1999

실시간 태스크의 최악 실행시간을 예측할 때 과예측이 발생하는 원인은, 첫째 프로그램의 동적인 최악 실행 행태를 정적으로 분석하는 것이 근본적으로 어렵기 때문이며, 둘째 최근의 RISC 형태 프로세서에 포함되어 있는 파이프라인 실행 구조와 캐쉬 등이 그러한 정적 분석을 더욱 어렵게 만들기 때문이다. 그런데 기존의 연구에서는 각각의 과예측 원인을 해결하기 위한 방법에 대해서만 언급하고 있을 뿐 분석의 정확도에서 각 원인이 차지하는 비중에 대해서는 언급하고 있지 않다. 이에 본 연구에서는 최악 실행시간 예측시 과예측을 유발하는 원인들, 즉 분석 요소들의 영향을 정량적으로 조사함으로써 기존의 최악 실행시간 분석 기법들이 보완해야 할 방향을 제시하고자 한다. 본 연구에서는 실험이 특정 분석 기법에 의존하지 않도록 하기 위하여 시뮬레이션 방법에 기반한다. 이를 위해 분석 요소별 스위치가 포함된 MIPS R3000 프로세서를 위한 시뮬레이터를 구현하였는데, 각 스위치는 해당 분석 요소에 대한 분석의 정확도 수준을 결정한다. 모든 스위치 조합에 대해서 시뮬레이션을 반복 수행한 다음 분산 분석을 수행하여 어떤 분석 요소가 가장 큰 영향을 끼치는지 고찰한다.Abstract Existing analysis techniques for estimating the worst case execution time (WCET) of real-time tasks still suffer from significant overestimation due to two types of overestimation sources. First, it is unavoidably difficult to predict dynamic behavior of programs statically. Second, pipelined execution and caching found in recent RISC-style processors even more complicate such a prediction. Although these overestimation sources have been attacked in many existing analysis techniques, we cannot find in the literature any description about questions like which one is most important. Thus, in this paper, we quantitatively analyze the impacts of overestimation sources on the accuracy of the worst case timing analysis. Using the results, we can identify dominant overestimation sources that should be analyzed more accurately to get tighter WCET estimations. To make our method independent of any existing analysis techniques, we use simulation based methodology. We have implemented a MIPS R3000 simulator equipped with several switches, each of which determines the accuracy level of the timing analysis for the corresponding overestimation source. After repeating simulation for all of the switch combinations, we perform the variance analysis and study which factor has the largest impact on the accuracy of the predicted WCETs.

• Journal of Computing Science and Engineering
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• v.8 no.1
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• pp.25-33
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• 2014

In this paper, we quantitatively compare two different time-predictable multicore cache architectures, separate and statically-partitioned caches, through extensive simulation. Current research trends primarily focus on partitioned-cache architectures in order to achieve time predictability for hard real-time multicore based systems, and our experiments reveal that separate caches actually lead to much better performance and energy efficiency when compared to statically-partitioned caches, and both of them are adequate for timing analysis for real-time multicore applications.

• Journal of Computing Science and Engineering
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• v.7 no.2
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• pp.89-98
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• 2013

This paper presents a complete survey of recent techniques that are applied in the field of real-time Java computing. It focuses on the issues that are especially important for hard real-time applications, which include time predictable garbage collection, worst-case execution time analysis of Java programs, real-time Java threads scheduling and compiler techniques designed for real-time purpose. It also evaluates experimental frameworks that can be used for researching real-time Java. This overview is expected to help researchers understand the state-of-the-art and advance the research in real-time Java computing.

• International Journal of Automotive Technology
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• v.5 no.4
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• pp.269-276
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• 2004

There has been considerable activity in recent years in developing timing analysis algorithms for distributed real-time control systems. However, it is difficult for control engineers to analyze the timing behavior of distributed real-time control systems because the algorithms was developed in a software engineer's position and the calculation of the algorithm is very complex. Therefore, there is a need to develop a timing analysis tool, which can handle the calculation complexity of the timing analysis algorithms in order to help control engineers easily analyze or develop the distributed real-time control systems. In this paper, an interactive timing analysis tool, called RAT (Response-time Analysis Tool), is introduced. RAT can perform the schedulability analysis for development of distributed real-time control systems. The schedulability analysis can verify whether all real-time tasks and messages in a system will be completed by their deadlines in the system design phase. Furthermore, from the viewpoint of end-to-end scheduling, RAT can perform the schedulability analysis for series of tasks and messages in a precedence relationship.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.1
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• pp.194-203
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• 2005

The process of guaranteeing that a distributed real-time control system will meet its timing constraints, is referred to as schedulability analysis. However, schedulability analysis algorithm cannot be simply used to analyze the system because of complex calculations of algorithm. It is difficult for control engineer to understand the algorithm because it was developed in a software engineer's position. In this paper we introduce a Response-time Analysis Tool(RAT) which provides easy way far system designer to analyze the system by encapsulating calculation complexity. Based on the RAT, control engineer can verify whether all real-time tasks and messages in a system will be completed by their deadline in the system design phase.

• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.