• Journal of Computing Science and Engineering
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• v.8 no.4
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• pp.215-227
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• 2014

In modern computer architectures, caches are widely used to shorten the gap between processor speed and memory access time. However, caches are time-unpredictable, and thus can significantly increase the complexity of worst-case execution time (WCET) analysis, which is crucial for real-time systems. This paper proposes a time-predictable two-level scratchpad-based architecture and an ILP-based static memory objects assignment algorithm to support real-time computing. Moreover, to exploit the load/store latencies that are known statically in this architecture, we study a Scratch-pad Sensitive Scheduling method to further improve the performance. Our experimental results indicate that the performance and energy consumption of the two-level scratchpad-based architecture are superior to the similar cache based architecture for most of the benchmarks we studied.

• Journal of Computing Science and Engineering
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• v.8 no.1
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• pp.34-42
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• 2014

Time-predictability of computing is critical for hard real-time and safety-critical systems. However, currently there is no metric available to quantitatively evaluate time-predictability, a feature crucial to the design of time-predictable processors. This paper first proposes the concept of architectural time-predictability, which separates the time variation due to hardware architectural/microarchitectural design from that due to software. We then propose the standard deviation of clock cycles per instruction (CPI), a new metric, to measure architectural time-predictability. Our experiments confirm that the standard deviation of CPI is an effective metric to evaluate and compare architectural time-predictability for different processors.

• Journal of Computing Science and Engineering
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• v.8 no.1
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• pp.25-33
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• 2014

In this paper, we quantitatively compare two different time-predictable multicore cache architectures, separate and statically-partitioned caches, through extensive simulation. Current research trends primarily focus on partitioned-cache architectures in order to achieve time predictability for hard real-time multicore based systems, and our experiments reveal that separate caches actually lead to much better performance and energy efficiency when compared to statically-partitioned caches, and both of them are adequate for timing analysis for real-time multicore applications.

• Journal of Computing Science and Engineering
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• v.7 no.2
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• pp.89-98
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• 2013

This paper presents a complete survey of recent techniques that are applied in the field of real-time Java computing. It focuses on the issues that are especially important for hard real-time applications, which include time predictable garbage collection, worst-case execution time analysis of Java programs, real-time Java threads scheduling and compiler techniques designed for real-time purpose. It also evaluates experimental frameworks that can be used for researching real-time Java. This overview is expected to help researchers understand the state-of-the-art and advance the research in real-time Java computing.

• Journal of Computing Science and Engineering
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• v.6 no.4
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• pp.267-278
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• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).

• Journal of Computing Science and Engineering
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• v.9 no.2
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• pp.51-72
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• 2015

Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.505-507
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• 2005

In this paper, a timing analysis is performed for the CAN-based simulator system for a fuel cell hybrid electric vehicles. The CAN protocol is recently being used for conventional vehicles, however, the network-induced delay can make the in-vehicle network system unstable. This problem may be occurred in the future vehicles because more ECUs are being required than recent vehicles. In order to develop a stable network-based control system, timing analysis is required at the design process. Throughout this analysis, timing parameters that affect transmission delay are examined and an effective method of predicting a sampling time for a stable communication via CAN protocol. In order to show the validityof suggested timing analysis. some experiments are performed using DSPs with CAN module.

• Journal of Computing Science and Engineering
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• v.5 no.1
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.445-450
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• 2007

NAND 플래시 메모리 기반의 실시간 임베디드 시스템에서는 일반적으로 shadowing 기법을 통해 프로그램을 수행한다. 그러나 shadowing 기법은 시스템의 부팅 시간을 증가시키고 불필요한 DRAM 영역을 차지한다는 단점 때문에 자원 제약이 심한 실시간 임베디드 시스템에는 적합하지 않다. 이에 대한 대안 중 하나는 demand paging 기법을 활용하는 것이다. 단, demand paging 환경에서는 page fault에 의한 시간 지연 때문에 태스크의 최악 실행 성능을 예측하기 어렵다. 따라서 본 논문에서는 NAND 플래시 메모리 기반의 실시간 임베디드 시스템에서 demand paging 비용을 고려한 태스크 최악 성능 분석 기법을 제안한다. 제안하는 기법은 각 태스크에 대해 demand paging 비용을 계산하고, 이를 전통적인 WCRT 분석 기법과 결합하는 방법을 사용한다. 또한 demand paging 비용과 WCET 분석을 독립적으로 고려함으로써, 최악의 경우에도 분석 결과의 안정성을 보장하고 기존의 방법에 비해 분석 복잡도를 줄였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.257-260
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• 2004

임베디드 시스템에 탑재될 자바가상머신을 기능별 모듈로 컴포넌트화 하여 이식될 플랫폼의 요구사항에 맞추어 재구성한다면 컴포넌트 기술의 장점인 소프트웨어의 재사용과 재구성을 통한 빠르고 신뢰성있는 자바가상머신 개발이 가능하다. 이러한 자바가상머신 컴포넌트 재구성을 위한 컴포넌트 모델의 정의 및 명세를 위한 지원도구가 필요하며, 명세도구의 지원 하에 보다 시각적인 컴포넌트 구성 및 각 명세요소 정의를 바탕으로 한 자바가상머신 컴포넌트의 재구성에 요구되는 여러 제약조건이나 각 컴포넌트 간의 관계정의 등이 명세 되어질 수 있다. 또한 임베디드 시스템이 가지는 실시간 속성에 대해서 정의하여 이를 명세도구를 통해서 속성명세 및 설계 시에 예측성을 지원하기 위한 WCET 계산이나 우선순위 정의 등을 명세할 수 있다. 따라서, 본 논문에서는 명세방법을 제안하고 실시간 속성 중심의 자바가상머신 컴포넌트 명세도구를 설계하고 구현하였으며, 기존에 제안된 내장형 실시간 컴포넌트 개발 도구와 비교하였다.