• KIPS Transactions on Computer and Communication Systems
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• 제5권1호
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.228-230
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• 2008

The response time characteristic of low voltage liquid crystals (LCs) is investigated and a new simulator for low voltage LCs is proposed. In order to enable low voltage operation, it is important to minimize Vth of LCs and variation of pixel voltage caused by dynamic capacitance operation of LC Display. Because dynamic capacitance variation is much larger for low voltage LC operation compared to that of conventional LC material, it is necessary to make a better model for dynamic capacitance operation. A proposed minimizing Vth of LCs and variation of pixel voltage study results through a new constant charge model improve response characteristics for low voltage LCs operation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제48권10호
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제21권4호
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제29권1호
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• pp.11-16
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• 2016

The conduction behavior and electron concentration change in a-IGZO thin-films according to the RTA (rapid thermal annealing) were studied. The electrical characteristics of TFTs (thin-film-transistors) annealed by different temperatures were measured. The sheet resistance, electron concentration, and oxygen vacancy of a-IGZO film were measured by the four-point-probe-measurement, hall-effect-measurement, and XPS analysis. The RTA process increased the driving current of IGZO TFTs but the VTH shifted to the negative direction at the same time. When the RTA temperature is higher than $250^{\circ}C$, the leakage current at off-state increased significantly. This is attributed to the increase of oxygen vacancy resulting in the increase of electron concentration. We demonstrate that the RTA is a promising process to adjust the VTH of TFT because the RTA process can easily modify the electron concentration and control the conductivity of IGZO film with short process time.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.256-256
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• 2016

기존의 디스플레이 기슬은 마스크를 통해 특정 부분에만 유기재료를 증착시키는 방법을 사용하였으나, 기판의 크기가 커짐에 따라 공정조건에 제약이 발생하였다. 이를 해결하기 위해 최근 용액 공정에 대한 연구가 활발히 진행되고 있다. 용액 공정은 기존 진공 증착 방식과 비교하였을 때 상온, 대기압에서 증착이 가능하며 경제적이고, 대면적 균일 증착에 유리하다는 장점이 있다. 반면, 용액 공정으로 제작한 소자는 시간이 지남에 따라 점차 전기적 특성이 변하는 aging effect를 보인다. Aging effect는 용액에 포함된 C기와 OH기 기반의 불순물의 영향으로 시간의 경과에 따라서 문턱전압, subthreshold swing 및 mobility 등의 전기적 특성이 변하는 현상으로 고품질의 박막을 형성하기 위해서는 고온의 열처리가 필요하다. 지금까지 고품질 박막 형성을 위한 열처리는 퍼니스 (furnace) 장비에서 주로 이루어졌는데, 시간이 오래 걸리고, 상대적으로 고온 공정이기 때문에 유리, 종이, 플라스틱과 같은 다양한 기판에 적용하기 어렵다는 단점이 있다. 따라서, 본 연구에서는 $100^{\circ}C$ 이하의 저온에서도 열처리가 가능한 microwave irradiation (MWI) 방법을 이용하여 solution-processed InGaZnO TFT를 제작하였고, 기존의 열처리 방식인 furnace로 열처리한 TFT 소자와 aging effect를 비교하였다. 먼저, solution-processed IGZO TFT를 제작하기 위해 p type Si 기판을 열산화시켜서 100 nm의 SiO2 게이트 산화막을 성장시켰고, 스핀코팅 방법으로 a-IGZO 채널층을 형성하였다. 증착후 열처리를 위하여 1000 W의 마이크로웨이브 출력으로 15분간 MWI를 실시하여 a-IGZO TFT를 제작하였고, 비교를 위하여 furnace N2 gas 분위기에서 $600^{\circ}C$로 30분간 열처리한 TFT를 준비하였다. 제작된 직후의 TFT 특성을 평가한 결과, MWI 열처리한 소자가 퍼니스 열처리한 소자보다 높은 이동도, 낮은 subthreshold swing (SS)과 히스테리시스 전압을 가지는 것을 확인하였다. 한편, aging effect를 평가하기 위하여 제작 후에 30일 동안의 특성변화를 측정한 결과, MWI 열처리 소자는 30일 동안 문턱치 전압(VTH)의 변화량 ${\Delta}VTH=3.18[V]$ 변화되었지만, furnace 열처리 소자는 ${\Delta}VTH=8.56[V]$로 큰 변화가 있었다. 다음으로 SS의 변화량은 MWI 열처리 소자가 ${\Delta}SS=106.85[mV/dec]$인 반면에 퍼니스 열처리 소자는 ${\Delta}SS=299.2[mV/dec]$이었다. 그리고 전하 트래핑에 의해서 발생하는 게이트 히스테리시스 전압의 변화량은 MWI 열처리 소자에서 ${\Delta}V=0.5[V]$이었지만, 퍼니스 열처리 소자에서 ${\Delta}V=5.8[V]$의 큰 수치를 보였다. 결과적으로 MWI 열처리 방식이 퍼니스 열처리 방식보다 소자의 성능이 우수할 뿐만 아니라 aging effect가 개선된 것을 확인할 수 있었고 차세대 디스플레이 공정에 있어서 전기적, 화학적 특성을 개선하는데 기여할 것으로 기대된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제10권1호
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• pp.111-116
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• 2006

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that Idark is $10^{-12}A$, Iphoto is $10^{-9}A$ and Iphoto/Idark is $10^3$, respectively. In the case of a-Si:H TFT, it indicates that Ion/Ioff is $10^6$, the drain current is a few ${\mu}A$ and Vth is $2\~4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 voltage in ITO of photodiode and $70{\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제33권1호
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• pp.6-9
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• 2020

Thin film transistors (TFTs) with large-area, high mobility, and high reliability are important factors for next-generation displays. In particular, thin transistors based on IGZO oxide semiconductors are being actively researched for this application. In this study, several methods for improving the reliability of a-IGZO TFTs by applying various materials on a passivation layer are investigated. In the literature, inorganic SiO₂, TiO₂, Al₂O₃, ZTSO, and organic CYTOP have been used for passivation. In the case of Al₂O₃, excellent stability is exhibited compared to the non-passivation TFT under the conditions of negative bias illumination stress (NBIS) for 3 wavelengths (R, G, B). When CYTOP passivation, SiO₂ passivation, and non-passivation devices were compared under the same positive bias temperature stress (PBTS), the Vth shifts were 2.8 V, 3.3 V, and 4.5 V, respectively. The Vth shifts of TiO₂ passivation and non-passivation devices under the same NBTS were -2.2 V and -3.8 V, respectively. It is expected that the presented results will form the basis for further research to improve the reliability of a-IGZO TFT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권4호
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• pp.45-52
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• 2009

We proposed a new pixel circuit and driving method for the large-area, high-luminance AMOLED applications in this study. We designed with the low-temperature poly-silicon(LTPS) thin film transistors(TFTs) that has poor uniformity but stable characteristic. To improve the uniformity of an image, the threshold voltage($V_{TH}$) and the mobility of the TFTs can be compensated together. The proposed method overcomes the previous methods for mobility compensation, and that is profitable for large-area applications. Black data insertion was introduced to improve the characteristics for moving images. AMOLED panel can operate in two compensation mode, so the luminance degradation by mobility compensation can be released. The scan driver for controlling the pixel circuits were optimized, and the compensation mode can be controlled simply by that. Final driving signal has large timing margin, and the panel operates stably. The pixel circuit was designed for 14.1" WXGA top-emission ANGLED panel. The non-uniformity of the designed panel was estimated under 5% for the mobility compensation time of 1us.

• Journal of IKEEE
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• 제17권2호
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• pp.214-220
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• 2013

Small area LDO (Low drop-out) regulator with pass transistor using body-driven technique is presented in this paper. The body-driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the pass transistor to reduce size of area and maintain the same performance as conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5 %. The proposed LDO regulator works under the input voltage of 2.7 V ~ 4.5 V and provides up to 150mA load current for an output voltage range of 1.2 V ~ 3.3 V.