• 전력전자학회논문지
• /
• 제27권2호
• /
• pp.106-117
• /
• 2022

Multiple output converters can be utilized when various output voltages are required in applications. Recently, one of the multiple output converters called fly-buck has been proposed, and has attracted attention due to the advantage that multiple output can be easily obtained with a simple structure. When constant on-time (COT) control is applied, the output ripple voltage must be treated carefully for control stability and voltage regulation characteristics in consideration of the inherent energy transfer characteristics of the fly-buck converter. This study analyzes the operation principle of the fly-buck converter with a ripple generation network and presents the design guideline for the improved output voltage regulation. Validity of the analysis and design guideline is verified using a 5 W prototype of the COT controlled fly-buck converter with a ripple generation network for telecommunication auxiliary power supply.

• 전력전자학회논문지
• /
• 제23권1호
• /
• pp.40-46
• /
• 2018

In this study, the output voltage balancing characteristics of parallel-input series-output (PISO) boost converter is analyzed. The PISO boost converter is derived by combining two basic boost converters. In comparison with the conventional three-level boost converter, the PISO boost converter can balance the output voltages under an unbalanced load condition without requiring additional circuit components and control strategy. A 2 kW prototype converter is built and tested to verify the output voltage balancing characteristics of the PISO boost converter.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2017년도 추계학술대회
• /
• pp.522-523
• /
• 2017

전류컨베이어 회로와 시간-디지털 변화기를 이용하여 아날로그-디지털 변환기를 설계하였다. 전류컨베이어 회로를 이용하여 아날로그 전압의 크기를 샘플링한 다음, 전류원을 이용하여 샘플링 전압을 방전하면서 아날로그 전압을 시간정보로 변환하였다. 시간정보는 카운터 타입의 시간-디지털 변환기를 이용하여 디지털 값으로 변환되는데 이때 변환 에러를 감소시키기 위해 시간정보 펄스와 동기화된 클록을 생성하여 사용하였다.

• Journal of Electrical Engineering and Technology
• /
• 제9권5호
• /
• pp.1551-1561
• /
• 2014

Design, Simulation and experimental analysis of closed loop time domain based Discrete PWM buck-boost converter are described. To improve the transient response and dynamic stability of the proposed converter, Discrete PID controller is the most preferable one. Discrete controller does not require any precise analytical model of the system to be controlled. The control system of the converter is designed using digital PWM technique. The proposed controller improves the dynamic performance of the buck-boost converter by achieving a robust output voltage against load disturbances, input voltage variations and changes in circuit components. The converter is designed through simulation using MATLAB/Simulink and performance parameters are also measured. The discrete controller is implemented, and design goal is achieved and the same is verified against theoretical calculation using LabVIEW.

• 전력전자학회논문지
• /
• 제20권2호
• /
• pp.130-136
• /
• 2015

This study describes the structure and operation modes of vertical stabilization (VS) converter for international thermonuclear experimental reactor (ITER) and proposes a protection method. ITER VS converter supplies voltage (${\pm}1000V$)/current (${\pm}22.5kA$) to superconducting magnets for plasma current vertical stabilization. A four-quadrant operation must be achieved without zero-current discontinuous section. The operation mode of the VS converter is separated in 12-pulse mode, 6-pulse mode and circulation current mode according to the magnitude of the load current. Protection measures, such as bypass and discharge, are proposed for abnormal conditions, such as over current, over voltage, short circuit, and voltage sag. VS converter output voltage is controlled to satisfy voltage response time within 20 msec. Bypass operation is completed within 60 msec and discharge operation is performed successfully. The feasibility of the proposed control algorithm and protection measure is verified by assembling a real controller and implementing a power system including the VS converter in RTDS for a hardware-in-loop (HIL) facility.

• Journal of Power Electronics
• /
• 제14권1호
• /
• pp.183-193
• /
• 2014

Due to the requirements for high reliability and accuracy, safety issues for airbag ignition systems need to be studied. In this paper, a high-voltage piezoelectric converter is designed to improve these requirements in airbag ignition systems. The proposed converter includes an inverter drive circuit, a Rosen piezoelectric transformer (PZT), an output circuit and a feedback control circuit. The key components of the high-voltage piezoelectric transformer are analyzed in detail. In addition, the proposed converter system is simulated and implemented for testing. The experimental results show that when the power supply is turned on, the charging time is less than 800ms. Furthermore, the output voltage of this converter can be kept between 2.9kV and 3.1kV, under high-efficiency constant current charging mode and zero-voltage switching conditions.

• 전력전자학회논문지
• /
• 제18권2호
• /
• pp.138-144
• /
• 2013

Most of the DC loads have had the sensitive characteristics electrically for input voltage. In this system, power converter is operated after connecting with DC loads to minimize the overshoot of the control voltage that may occur during connection of the loads. But whenever starting the power converter, parameters in circuit are different because power converter has been connected with diverse load types at each startup time. This is cause of a disadvantage to PI controller design of power converter. In this paper, the novel voltage control method using sliding mode control theory has proposed. This control method minimizes the overshoot of control voltage at startup of power converter. Despite the variations of the system parameters, the proposed voltage controller has fast response and robustness characteristics such as PI and sliding mode controllers. The proposed controller was applied to the three-phase AC/DC converter and each performance of controller was verified.

• Journal of Power Electronics
• /
• 제11권2호
• /
• pp.113-119
• /
• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• Journal of Power Electronics
• /
• 제19권1호
• /
• pp.34-43
• /
• 2019

An improved half-bridge LLC converter with a magamp auxiliary post-regulator is proposed in this paper. The function of the magamp is bypassed when the converter works within the low input-voltage range. Meanwhile, it operates as an auxiliary post-regulator when the input voltage is high. By changing the blocking time of the magamp, the dc gain of the converter can be extended. Hence, the input voltage range of the converter is extended. The realization of proposed topology does not require a complicated circuit. The controller of the magamp can be easily implemented using only passive components, transistors and an OP amp. The generalized operational principle is analyzed and the design criterion for the magamp is presented. Finally, a 25V output, 400W experimental prototype was built and tested for a 160-300V input-voltage range to verify the feasibility of the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권4호
• /
• pp.411-417
• /
• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.