• Journal of Power Electronics
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• v.11 no.6
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Journal of Power Electronics
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• v.17 no.3
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• pp.664-673
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• 2017

With the development of multilevel converters, cascaded single-phase H-bridge rectifiers (CHBRs) has become widely adopted in high-voltage high-power applications. In this study, sequence pulse modulation (SPM) is proposed for CHBRs. SPM is designed to balance the dc-link voltage and maintain the smooth changes of switch states. In contrast to phase disposition modulation, SPM balances the dc-link voltage even after removing the load of one submodule. The operation principle of SPM is deduced, and the unbalance degree of SPM is analyzed. All the proposed approaches are experimentally verified through a prototype of a four-module (nine-level) CHBR. Conclusions are drawn in accordance with the results of SPM and its imbalance degree analysis.

• Journal of Power Electronics
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• v.15 no.2
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• pp.389-398
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• 2015

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

• Journal of IKEEE
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• v.17 no.3
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.606-610
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• 2003

This paper presents a simple carrier symmetric method for the voltage balance of flying capacitors in FCMLI(flying capacitor multi-level inverter). To achieve the voltage balance of flying capacitors, the utilization of each carrier must be balanced during a half-cycle of the switching period such as PSPWM(Phase-Shifted PWM). However, the CRPWM(Carrier Redistribution PWM) method causes the fluctuation of flying capacitor voltages because the balanced utilization of carriers is not achieved. Moreover, it does not consider that the load current change has an influence on flying capacitor voltages by assuming that the current flows Into the load. To overcome the drawbacks of CRPWM, it is modified by the technique that carriers of each band are disposed symmetrically at every fundamental period. Firstly, the CRPWN method is reviewed and the theory on voltage balance of flying capacitors is analyzed. The proposed method Is introduced and is verified through the experiment result.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.2
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• pp.83-88
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• 1999

Series connection of power semiconductor devices is selected in high voltage and high power applications. It is important to prevent the overvoltage from being induced across a device above ratings by the proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by controlling the slope of collector voltage under the turn-off transient in the series connected IGBTs. The proposed gate control scheme changes the slope of collector voltage by sensing the collector voltage and controlling the gate signal actively. The new series connected IGBT gate driver is made and its validity is verified by the experimental results for series connected IGBT circuit.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.9 no.2
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• pp.35-41
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• 2010

The balance coefficients between telecommunication lines are specified in the technical standard and the power induction computation method varies in the order of 100 times in magnitude according to the amount of impedance. The results of actual balance measurements, differing from time to time with the measurement circuit or increasing proportionally as the induction voltage increases, appeared as a measurement error because of not using the standard measurement circuit. This article investigates such errors and proposes the use of a standard balance measurement circuit and a measurement device impedance under the domestic notification standard and the ITU-T international standard.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.316-317
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• 2018

This paper propse the DC link capacitor voltage balancing control for three level neutral point clamped converter with harmonic component injection method. The injcetion voltage consists of harmonic component and DC link capacitor voltage difference. Theoretical analysis is provided to balance the DC link voltage, and it shows that harmonic component compensates the unbalanced condition between the capacitors. Both simulations and experiments are carried out to show that the voltage unbalance have been decreased by the proposed method.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.843-847
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• 2014

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.